ADS5525 datasheet(39/57 Pages) TI

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Power Scaling Modes

Power Supply Sequence

Digital Output Information

Output Interface

DDR LVDS Outputs

ADS5547

SLWS192A – NOVEMBER 2006 – REVISED MAY 2007

ADS5547 has a power scaling mode in which the device can be operated at reduced power levels at lower

sampling frequencies with no difference in performance. (See Figure 27)(1) There are four power scaling modes

for different sampling clock frequency ranges, using the serial interface register bits <SCALING> (Table 16).

Only the AVDD power is scaled, leaving the DRVDD power unchanged.

Table 20. Power Scaling vs Sampling Speed

Sampling Frequency

Analog Power

Power Scaling Mode

Analog Power in Default Mode

MSPS

(Typical)

> 150

Default

1010 mW at 210 MSPS

105 to 150

Power Mode 1

841 mW at 150 MSPS

917 mW at 150 MSPS

50 to 105

Power Mode 2

670 mW at 105 MSPS

830 mW at 105 MSPS

< 50

Power Mode 3

525 mW at 50 MSPS

760 mW at 50 MSPS

(1)

The performance in the power scaling modes is from characterization and not tested in production.

During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are

separated inside the device. Externally, they can be driven from separate supplies or from a single supply.

ADS5547 provides 14-bit data, an output clock synchronized with the data and an out-of-range indicator that

goes high when the output reaches the full-scale limits. In addition, output enable control (OE pin 7) is provided

to power down the output buffers and put the outputs in high-impedance state.

Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be

selected using the DFS (see Table 6) or the serial interface register bit <ODI> (Table 15).

In this mode, the 14 data bits and the output clock are available as LVDS (Low Voltage Differential Signal)

levels. Two successive data bits are multiplexed and output on each LVDS differential pair as shown in

Figure 47. So, there are 7 LVDS output pairs for the 14 data bits and 1 LVDS output pair for the output clock.

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