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TMS320DM647 Datasheet(PDF) 120 Page - Texas Instruments |
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TMS320DM647 Datasheet(HTML) 120 Page - Texas Instruments |
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120 / 166 page ![]() www.ti.com 6.15 Host-Port Interface (HPI) Peripheral 6.15.1 HPI Device-Specific Information 6.15.2 HPI Peripheral Register Description(s) TMS320DM647/TMS320DM648 Digital Media Processor SPRS372 – MAY 2007 The DM647/DM648 devices include a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32). The AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit peripheral. Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the DM647/DM648. An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0. Table 6-50. HPI Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0x0200 0000 - Reserved PWREMU_MGMT has both 0x0200 0004 PWREMU_MGMT HPI power and emulation management register host/CPU read/write access. 0x0200 0008 - 0x0200 0024 - Reserved 0x0200 0028 - Reserved 0x0200 002C - Reserved The host and the CPU have 0x0200 0030 HPIC HPI control register read/write access to the HPIC register.(1) HPIA HPI address register The host has read/write 0x0200 0034 (HPIAW)(2) (Write) access to the HPIA registers. The CPU has only read HPIA HPI address register 0x0200 0038 access to the HPIA registers. (HPIAR)(2) (Read) 0x0200 000C - 0x0200 007F - Reserved 0x0200 0080 - 0x0200 FFFF - Reserved (1) The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an interrupt from the host. (2) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes, see theTMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5). 120 Peripheral Information and Electrical Specifications Submit Documentation Feedback |
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