Philips Semiconductors

Product data

PCA9559

5-bit multiplexed/1-bit latched 6-bit

2003 Jun 27

7

AC CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

MUX_IN

⇒ MUX_OUT

LOW-to-HIGH transition time

—

28

37

ns

HIGH-to-LOW transition time

—

16

21

ns

Select

⇒ MUX_OUT

tPLH

LOW-to-HIGH transition time

—

30

39

ns

tPHL

HIGH-to-LOW transition time

—

17

22

ns

OVERRIDE_N

⇒ NON-MUXED_OUT

LOW-to-HIGH transition time

—

34

43

ns

HIGH-to-LOW transition time

—

19

25

ns

OVERRIDE_N

⇒ MUX_OUT

LOW-to-HIGH transition time

—

31

41

ns

HIGH-to-LOW transition time

—

21

27

ns

Output rise time

1.0

—

3

ns/V

Output fall time

1.0

—

3

ns/V

Pull-up resistor for outputs

1.0

—

—

ns/V

Test load capacitance on outputs

—

—

—

pF

SCL clock frequency

10

—

400

kHz

Bus free time between a STOP and a START condition

1.3

—

—

µs

Hold time (repeated) START condition. After this period, the first

clock pulse is generated

600

—

—

ns

LOW period of SCL clock

1.3

—

—

µs

HIGH period of SCL clock

600

—

-12

ns

Set-up time for a repeated START condition

600

—

-32

ns

Data hold time

0

—

10

ns

Data set-up time

100

—

-100

ns

Data spike time

0

—

50

ns

Set-up time for STOP condition

600

—

10

ns

Rise time for both SDA and SCL signals (10 - 400 pF bus)

20

—

300

ns

Fall time for both SDA and SCL signals (10 - 400 pF bus)

20

—

300

ns

Capacitive load for each bus line

—

—

400

pF

—

15

—

ms

NOTE: