PCB2421 datasheet(5/24 Pages) PHILIPS

5 / 24 page

1997 Apr 01

Philips Semiconductors

Preliminary speciﬁcation

1K dual mode serial EEPROM

PCB2421

FUNCTIONAL DESCRIPTION

The PCB2421 operates in two modes, the transmit-only

mode (DDC1) and the bidirectional mode (DDC2, or

I2C-bus mode). There is a separate two-wire protocol to

support each mode, each having a separate clock input

and sharing a common data line (SDA). The device enters

the transmit-only mode (DDC1) upon power-up. In this

mode the device transmits data bits on the SDA pin in

response to a clock signal on the VCLK pin. The device will

remain in this mode until a valid HIGH-to-LOW transition is

placed on the SCL input. When a valid transition on SCL is

recognized, the device will switch into the bidirectional

mode (see Fig.3). The only way to switch the device back

to the transmit-only mode (DDC1) is to remove power from

the device.

6.1

Transmit-only mode (DDC1)

The device will power-up in the transmit-only mode. This

mode supports a unidirectional two-wire protocol for

transmission of the contents of the memory array

(see Fig.12). The PCB2421 requires that it be initialized

prior to valid data being sent in the transmit-only mode

(see Section “Initialization procedure”, and Fig.4).

In this mode, data is transmitted on the SDA pin in 8-bit

bytes, each byte followed by a ninth clock pulse during

which time SDA is left high-impedance. The clock source

for the transmit-only mode is provided on the VCLK pin;

a data bit is output on the rising edge on this pin. The 8 bits

in each byte are transmitted most significant bit first. Each

byte within the memory array will be output in sequence.

When the last byte in the memory array is transmitted, the

output will wrap around to the first location and continue.

The bidirectional mode clock (SCL) pin must be held HIGH

for the device to remain in the transmit-only mode.

6.2

Initialization procedure

At power-on, after VDD has stabilized, the device will be in

the transmit-only mode. Nine clock cycles on the VCLK pin

must be given to the device for it to perform internal

synchronization. During this period, the SDA pin will be in

a high-impedance state. On the rising edge of the tenth

clock cycle, the device will output the first valid data bit

which will be the most significant bit of a byte. The device

will power-up with address pointer at 00H (see Fig.4).

6.3

Bidirectional mode (DDC2B, I2C-bus mode)

The PCB2421 can be switched into the bidirectional mode

(see Fig.3) by applying a valid HIGH-to-LOW transition on

the bidirectional mode clock (SCL).

When the device has been switched into the bidirectional

mode, the VCLK input is disregarded. This mode supports

a two-wire bidirectional data transmission protocol

(I2C-bus protocol). In the I2C-bus protocol, a device that

sends data on the bus is defined to be the transmitter, and

a device that receives data from the bus is defined to be

the receiver. The bus must be controlled by a master

device that generates the bidirectional mode clock,

controls access to the bus, and generates the START and

STOP conditions, while the PCB2421 acts as slave. Both

master and slave can operate as transmitter or receiver,

but the master device determines which mode is activated.

6.3.1

BIDIRECTIONAL MODE BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is not

busy

• During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data

line while the clock line is HIGH will be interpreted as a

START or STOP condition.

Accordingly, the following bus conditions have been

defined (see Fig.6).

6.3.2

BUS NOT BUSY (A)

Both data (SDA) and clock (SCL) lines remain HIGH.

6.3.3

START CONDITION (B)

A HIGH-to-LOW transition of the SDA line while SCL is

HIGH determines a START condition. All commands must

be preceded by a START condition.

6.3.4

STOP CONDITION (C)

A LOW-to-HIGH transition of the SDA line while SCL is

HIGH determines a STOP condition. All operations must

be ended with a STOP condition.

6.3.5

DATA VALID (D)

The state of the data line represents valid data when, after

a START condition, the data line is stable for the duration

of the HIGH period of the clock signal. The data on the line

must be changed during the LOW period of the clock

signal. There is one clock pulse per bit of data. Each data

transfer is initiated with a START condition and terminated

with a STOP condition. The maximum number of data

bytes transferred between the START and STOP

conditions during a write operation is 8 bytes (see Section

“Page write” and Fig.5).

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