VT6306L datasheet(34/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

-28-

PHY Control Registers

Memory Offset EC – PHY Control................................. RW

This register is used to read or write a PHY register. To read

or write, the address of the register is written into the Register

Address field. For reads the “Read Register” bit is set (when

the request has been sent to the PHY, the “Read Register” bit

is cleared automatically by the chip). When transmitting the

request, the first clock for LREQ for the register read/write

portion will be bit-11 of this register followed by bit-10, etc,

finishing with bit-8 for register reads and bit-0 for register

writes. When the PHY returns the register through a status

transfer, the “Read Done” bit is set.

The address of the

contents in the “Read Data” field.

The first bits of data

received on the status transfer for the register are placed in bits

27 (D[0]) and 26 (D[1]) of this register. For writes, the value

to write is written to the “Write Data” field and the “Write

The “Write Register” bit is cleared

automatically by the chip when the write request has been sent

to the PHY.

Read Done

Indicates that a read request has been completed and

valid information is contained in the Read Data and

Read Address fields.

Cleared when the “Read

It is set by the chip when a

30-28 Reserved

........................................ always reads 0

27-24 Read Address

The address of the register most recently received

from the PHY.

23-16 Read Data

The contents of the register most recently received

from the PHY

Read Register

Used to initiate a read request from a PHY register

(must not be set at the same time as the “Write

has been sent.

Write Register

Used to initiate a write request to a PHY register

(must not be set at the same time as the “Read

has been sent.

13-12 Reserved

........................................ always reads 0

11-8 Register Address

The address of the PHY register to be read or written

7-0

Write Data

The data to be written to the PHY (ignored for reads)

Cycle Timer Registers

Memory Offset F0 – Isochronous Cycle Timer .............. RW

This register shows the current cycle number and offset.

When the chip is cycle master, this register is transmitted with

the cycle start message.

When it is not cycle master, this

In the event that the cycle start message is not received, the

fields continue incrementing on their own (when the “Cycle

Timer Enable” field is set in the “Link Control” register) to

maintain a local time reference.

31-25 Cycle Seconds

...........................................default = 0

This field counts seconds (“Cycle Count” rollovers)

modulo 128.

24-12 Cycle Count

..............................................default = 0

This field counts cycles (“Cycle Offset” rollovers)

modulo 8000.

11-0 Cycle Offset

..............................................default = 0

This field counts 24.576 MHz clocks modulo 3072

(125 usec).

VT6306L Datasheet(PDF) 34 Page - VIA Technologies, Inc.

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