PCE84C487 datasheet(21/36 Pages) PHILIPS

21 / 36 page

1996 Feb 21

Philips Semiconductors

Objective speciﬁcation

Microcontrollers for digital auto-sync and

VST TV controller applications

PCE84C486; PCE84C487

9I2C-BUS INTERFACE

The PCE84C48X has an on-chip I2C-bus interface that

can be used in master or slave mode. Full details of the

I2C-bus are given in the document

“The I2C-bus and how

to use it”. This document may be ordered using the code

9398 393 40011.

The I2C-bus interface lines SDA and SCL share the same

pins as port lines DP20 and P10 respectively. Selection of

the pin function as either an I2C-bus line or a port line is

achieved using the SDAE and SCLE bits in Derivative

these pins.

10 8-BIT COUNTER (T3)

The main application for this counter is in the frequency

measurement of the Hsync signal.

The block diagram of the 8-bit counter is shown in Fig.22.

A Schmitt trigger is used at the input for noise rejection and

also to shape the input signal into a square wave. The T3

input is sampled at a frequency of 1

⁄3 × fosc by the sample

clock which synchronizes the internal T3 clock and the

read operation of Derivative Register 24. The rising edge

of the input increments the ripple counter by 1.

The contents of T3 may be read using the instruction

MOV A, D24H. As soon as the data is read, the counter is

reset to zero. A counter overflow or Power-on-reset also

resets the counter contents to zero.

If the rising and falling edges of the input pulse are less

than 30 ns then the minimum pulse width that the T3 input

will recognise is 3/fosc + 100 ns. If the system clock is

10 MHz then the minimum pulse width is 400 ns. In some

display modes, the active pulse width of the Hsync signal

can be less than 400 ns; in this situation some external

application circuitry may be required.

handbook, halfpage

0.9 V

0.1 V

0.9 V

MGC719

Fig.18 T3 input waveform.

Fig.19 Block diagram of the 8-bit counter (T3).

handbook, full pagewidth

MGC717

Power-on-reset

sample clock

READ D24H

EMU

8-BIT COUNTER

RESET

Q0 to Q7

Data bus

SYNCHRONISATION

CIRCUIT

T3 COUNTER

CONTROL CIRCUIT

PCE84C487 Datasheet(PDF) 21 Page - NXP Semiconductors

PCE84C487 Datasheet(HTML) 21 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL