ZSP540 - Highly Efficient

Quad-MAC DSP Core

OVER VIEW

The ZSP540 processor core is a high-performance/power-efficient Quad-

16-bit architecture with extensive 32-bit capabilities and sets an unmatched

balance of performance/power/size and memory utilization efficiency. The

Z.Turbo feature provides the SOC designer with the option to extend the ZSP540

Instruction Set and the ability to add application-specific acceleration logic.

T ARGET MARKETS

•

2.5/3G wireless baseband processing

•

Multimedia wireless and mobile devices

•

Cable/xDSL

•

Wireless LAN (WLAN)

•

Set-top box and home gateways

•

Multi-channel Voice Over IP (VoIP)

•

Software Defined Radio (SDR)

APPLICA TION BENEFITS

•

High-performance DSP capabilities

•

Excellent power/cost/speed balance

•

Excellent multimedia audio/video processing

•

Power efficient baseband processing performance

•

DSP and system control functions handling capabilities

CORE FEA TURES

• Quad-MAC/Six-ALU DSP core

• 4+1 instructions per cycle

• Up to 350MHz, 8-stage pipeline design

• Up to 1750 million instructions/sec

• Dual 64-bit wide Load/Store data ports

• Z.Turbo coprocessor extensions capable

• 24-bit address space

• HW managed instructions scheduling

• HW/SW controlled power management

• Real-time trace and profiling capability

• Full AMBA/AHB support (optional)

• JTAG debug interface

• Static, single phase clocked design

• Compatible with all other ZSP cores

ARCHITECTURE FEA TURES

• Embedded control processing efficiency

• 32-bit addressing capabilities

• 16 and 32-bit standard instruction set

• Extensive 32-bit and 40-bit support

• Easy to program instruction set

• Load/store register based instructions

• Outstanding code density

• User extensible instruction set

SUPPOR T

• Highly optimized C-compiler

• Multimedia, voice and wireless experts

• Local support by ZSP solution experts

40-bit

ALU

16x16

MAC

16x16

MAC

Multiply/ALU Unit 0

40-bit

ALU

16x16

MAC

16x16

MAC

Multiply/ALU Unit 1

Bypass Logic

16-bit

ALU

16-bit

ALU

Timers

ALU Unit

Pipeline

Control Unit

(PCU)

Register File

Instruction

Sequence Unit

(ISU)

Prefetch Unit (PFU)

Interrupt Control

Co-Processor IF

Debug IF

File

Instruction Cache

Load/Store Unit (LSU)

Dual AGU

128-bit

64-bit

64-bit