Philips Semiconductors

Product specification

74ABT573A

Octal D-type transparent latch (3-State)

1995 Sep 06

2

LOGIC SYMBOL (IEEE/IEC)

1

11

2

3

4

5

6

7

8

9

EN

C1

2D

1

19

18

17

16

15

14

13

12

SA00187

LOGIC SYMBOL

234

56789

11

1

E

OE

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

19

18

17

16

15

14

13

12

SA00186

FUNCTION TABLE

INPUTS

INTERNAL

OUTPUTS

OPERATING MODE

OE

E

Dn

REGISTER

Q0 – Q7

L

L

H

H

L

H

L

H

L

H

Enable and read register

L

L

↓

↓

l

h

L

H

L

H

Latch and read register

L

L

X

NC

NC

Hold

H

H

L

H

X

Dn

NC

Dn

Z

Z

Disable outputs

H = High voltage level

h

= High voltage level one set-up time prior to the High-to-Low E transition

L

= Low voltage level

l

= Low voltage level one set-up time prior to the High-to-Low E transition

NC= No change

X = Don’t care

Z = High impedance “off” state

↓ = High-to-Low E transition

LOGIC DIAGRAM

EQ

D

2

D0

Q0

EQ

D

3

D1

EQ

D

4

D2

EQ

D

5

D3

EQ

D

6

D4

EQ

D

7

D5

EQ

D

8

D6

EQ

D

9

D7

19

Q1

18

Q2

17

Q3

16

Q4

15

Q5

14

Q6

13

Q7

12

11

E

1

OE

SA00188