SN74LS156 datasheet(3/4 Pages) ONSEMI

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SN74LS156

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LOGIC DIAGRAM

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

Ea Ea

Eb Eb

O0a

O1a

O2a

O3a

O0b

O1b

O2b

O3b

FUNCTIONAL DESCRIPTION

The LS156 is a Dual 1-of-4 Decoder/Demultiplexer with

common Address inputs and separate gated Enable inputs.

When enabled, each decoder section accepts the binary

weighted Address inputs (A0, A1) and provides four

mutually exclusive active LOW outputs (O0 –O3). If the

Enable requirements of each decoder are not met, all outputs

of that decoder are HIGH.

Each decoder section has a 2-input enable gate. The

enable gate for Decoder “a” requires one active HIGH input

and one active LOW input (Ea•Ea). In demultiplexing

applications, Decoder “a” can accept either true or

complemented data by using the Ea or Ea inputs respectively.

The enable gate for Decoder “b” requires two active LOW

inputs (Eb•Eb). The LS155 or LS156 can be used as a 1-of-8

Decoder/Demultiplexer by tying Ea to Eb and relabeling the

common connection as (A2). The other Eb and Ea are

connected together to form the common enable.

The LS156 can be used to generate all four minterms of

two variables. These four minterms are useful in some

applications replacing multiple gate functions as shown in

Fig. a. The LS156 has the further advantage of being able to

AND the minterm functions by tying outputs together. Any

number of terms can be wired-AND as shown below.

f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅

(E + A0 + A1)

where E = Ea + Ea; E = Eb + Eb

Figure a

TRUTH TABLE

ADDRESS

ENABLE “a”

OUTPUT “a”

ENABLE “b”

OUTPUT “b”

H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

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