PCF8548USLASH2 datasheet(23/40 Pages) PHILIPS

23 / 40 page

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8548

Notes

1. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load.

2. Internal clock.

3. When fsclk = 0 there is no I2C-bus clock.

4. Power-down mode. During power-down all static currents are switched off.

5. If external VLCD, the display load current is not transmitted to IDD.

6. Tolerance depends on the temperature; (typically zero at Tamb =27 °C), maximum tolerance values are measured

at the temperature range limit.

7. For TC0 to TC3.

IDD(tot)

total supply current

with internal VLCD generation;

VDD1 = 2.8 V; VLCD = 7.6 V;

fsclk = 0; Tamb =25 °C; no

display load; 4

× charge pump;

notes 2 and 3

−

200

350

µA

(Power-down mode) with

internal or external VLCD

generation; note 4

−

1.5

µA

ILCDIN

supply current from

external VLCD

VDD1 = 2.8 V; VLCD = 7.6 V;

fsclk = 0; Tamb =25 °C; no

display load; notes 2, 3 and 5

−

−µA

Logic

VIL

LOW-level input voltage

VSS1

−

0.3VDD1

VIH

HIGH-level input voltage

0.7VDD1

−

VDD1

leakage current

Vi =VDD1 or VSS1

−1

−

µA

Column and row outputs

Rrow

row output resistance

R0 to R64

VDD1 to VDD3 = 5.0 V;

VLCD = 7.6 V; IL =10 µA;

outputs tested one at a time

−

Ω

Rcol

column output

resistance C0 to C101

VLCD = 7.6 V

−

Ω

Vbias(col)

column bias tolerance

C0 to C101

−100

+100

Vbias(row)

row bias tolerance

R0 to R64

−100

+100

LCD supply voltage generator

VLCD

VLCD tolerance

internally generated

VDD1 = 2.8 V; VLCD = 7.6 V;

fsclk = 0; Tamb =25 °C;

no display load;

notes 2, 3 6 and 7

−300

+300

temperature coefﬁcient

−−0.0 × 10−3

−

°C

−−0.76 × 10−3 −

°C

−−1.05 × 10−3 −

°C

−−2.10 × 10−3 −

°C

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

PCF8548U/2 Datasheet(PDF) 23 Page - NXP Semiconductors

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