5

AT93C46

5140B–SEEPR–2/07

Note:

The Xs in the address field represent DON’T CARE values and must be clocked.

Functional

Description

The AT93C46 is accessed via a simple and versatile three-wire serial communication

interface. Device operation is controlled by seven instructions issued by the host pro-

cessor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic

“1”) followed by the appropriate op code and the desired memory address location.

READ (READ): The Read (READ) instruction contains the address code for the mem-

ory location to be read. After the instruction and address are decoded, data from the

selected memory location is available at the serial output pin DO. Output data changes

are synchronized with the rising edges of serial clock SK. It should be noted that a

dummy bit (logic “0”) precedes the 8- or 16-bit data output string.

ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes

into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write

Enable (EWEN) instruction must be executed first before any programming instructions

can be carried out. Please note that once in the EWEN state, programming remains

ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified

memory location to the logical “1” state. The self-timed erase cycle starts once the

Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status

logic “1” at pin DO indicates that the selected memory location has been erased and the

part is ready for another instruction.

WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be

after the last bit of data is received at serial data input pin DI. The DO pin outputs the

Read/Busy status of the part if CS is brought high after being kept low for a minimum of

indicates that the memory location at the specified address has been written with the

data pattern contained in the instruction and the part is ready for further instructions. A

Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-

timed programming cycle tWP.

Table 5. Instruction Set for the AT93C46

Instruction

SB

Op

Code

Address

Data

Comments

x 8

x 16

x 8

x 16

READ

1

10

Reads data stored in memory, at

specified address

EWEN

1

00

11XXXXX

11XXXX

Write enable must precede all

programming modes

ERASE

1

11

WRITE

1

01

ERAL

1

00

10XXXXX

10XXXX

Erases all memory locations. Valid

WRAL

1

00

01XXXXX

01XXXX

Writes all memory locations. Valid

EWDS

1

00

00XXXXX

00XXXX

Disables all programming instructions