Philips Semiconductors

Product specification

PCK2014A

CK98 (100/133 MHz) spread spectrum

system clock generator

2001 Apr 02

9

3V66 CLOCK OUTPUT, 3V66 (0–1) (LUMP CAPACITANCE TEST LOAD = 30 pF)

SYMBOL

PARAMETER

LIMITS

LIMITS

UNIT

NOTES

SYMBOL

PARAMETER

133 MHz MODE

100 MHz MODE

UNIT

NOTES

MIN

MAX

MIN

MAX

3V66 CLK period

15.0

15.3

15.0

15.3

ns

2, 9, 4

3V66 CLK HIGH time

4.95

n/a

4.95

n/a

ns

5, 10

3V66 CLK LOW time

4.55

n/a

4.55

n/a

ns

6, 10

3V66 CLK rise time

0.5

2.0

0.5

2.0

ns

8

3V66 CLK fall time

0.5

2.0

0.5

2.0

ns

8

3V66 CLK cycle-cycle jitter

500

500

ps

DUTY CYCLE

3V66 CLK Duty Cycle

45

55

45

55

%

1

3V66 CLK pin-pin skew

250

250

ps

2

48MHZ CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20 pF)

SYMBOL

PARAMETER

LIMITS 133 MHz

LIMITS 100 MHz

UNIT

NOTES

MIN

MAX

MIN

MAX

48 MHz clock period average

20.83

20.83

20.83

20.83

ns

2

48 MHz clock HIGH time

7.57

n/a

7.57

n/a

ns

48 MHz clock LOW time

7.17

n/a

7.17

n/a

ns

Output rise edge rate

1

4

1

4

ns

Output fall edge rate

1

4

1

4

ns

Duty Cycle

45

55

45

55

%

CLK cycle-cycle jitter

500

500

ps

Frequency stabilization from Power-up (cold start)

3

ms

NOTE:

1. See Figure 5 for measure points.

2. Average period over 1

µs.