PCK2021 datasheet(10/15 Pages) PHILIPS

10 / 15 page

Philips Semiconductors

Product data

PCK2021

CK00 (100/133 MHz) spread spectrum differential

system clock generator

2001 Oct 11

Group offset limits

GROUP

OFFSET

MEASUREMENT LOADS

(LUMPED)

MEASUREMENT POINTS

NOTES

3V66 to PCI

0–500 ps, 3V66 leads

30 pF

1.5 V

18, 19

NOTES TO THE AC TABLES:

1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels.

2. Period, jitter, offset, and skew measured on rising edge at 1.5 V for 3.3 V clocks.

3. PCI is a fixed 33 MHz and 3V66 is a fixed 66 MHz.

4. Frequency accuracy of 48 MHz must be +167 ppm to match USB default.

5. tHIGH is measured at 2.4 V for 3.3 V outputs, as shown in Figure 7.

6. tLOW is measured at 0.4 V for all outputs as shown in Figure 7.

7. the time is specified from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable

and operating within specification.

8. tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification.

9. The average period over any 1

µs period of time must be greater than the minimum specified period.

10. Calculated at minimum edge rate (1 V/ns) to guarantee 45–55% duty cycle. Pulse width is required to be wider at faster edge rate to ensure

duty specification is met.

11. Test load is RS = 33.2 Ω, RP = 49.9 Ω.

12. Must be guaranteed in a realistic system environment.

13. Configured for VOH = 0.71 V in a 50 Ω environment.

14. Measured at crossing points.

15. Measured at 20% to 80%.

16. Frequency generated by crystal oscillator

17. Voltage measure point (VM = 1.5 V).

18. All offsets are to be measured at rising edges.

19. Parameters are guaranteed by design.

PCK2021 Datasheet(PDF) 10 Page - NXP Semiconductors