PCK2057 datasheet(2/12 Pages) PHILIPS

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Philips Semiconductors

Product data

PCK2057

70 – 190 MHz I2C differential 1:10 clock driver

2001 Jun 12

853–2253 26485

FEATURES

• Optimized for clock distribution in DDR (Double Data Rate)

SDRAM applications supporting DDR 200/266/300/333

• Full DDR solution provided when used with PCK2002P or

PCK2002PL, and PCK2022RA

• 1-to-10 differential clock distribution

• Very low jitter (< 100 ps)

• Operation from 2.2 V to 2.7 V AV

DD and 2.3 V to 2.7 V VDD

• SSTL_2 interface clock inputs and outputs

• HCSL to SSTL_2 input conversion

• Test mode enables buffers while disabling PLL

• Tolerant of Spread Spectrum input clock

• 3.3 V I2C support with 3.3 V V

DDI

• 2.5 V I2C support with 2.5 V V

DDI

• Form, fit, and function compatible with CDCV850

DESCRIPTION

The PCK2057 is a high-performance, low-skew, low-jitter zero delay

buffer that distributes a differential clock input pair (CLK, CLK) to ten

differential pairs of clock outputs and one differential pair of

feedback clock outputs. The clock outputs are controlled by the

clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the

2-line serial interface (SDA, SCL), and the analog power input

(AVDD). The two-line serial interface (I2C) can put the individual

output clock pairs in a high-impedance state. When AVDD is tied to

GND, the PLL is turned off and bypassed for test purposes.

The device provides a standard mode (100 kbits) I2C interface for

device control. The implementation is as a slave/receiver. The serial

inputs (SDA, SCL) provide integrated pull-up resistors (typically

100 k

Ω).

Two 8-bit, 2-line serial registers provide individual enable control for

each output pair. All outputs default to enabled at power-up. Each

output pair can be placed in a high-impedance mode, when a

low-level control bit is written to the control register. The registers

must be accessed in sequential order (i.e., random access of the

registers is not supported). The I2C interface circuit can be supplied

with either 2.5 V or 3.3 V (VDDI2C).

Since the PCK2057 is based on PLL circuitry, it requires a

stabilization time to achieve phase-lock of the PLL. This stabilization

time is required following power-up.

PIN CONFIGURATION

GND

VDDQ

GND

VDDQ

SCL

CLK

VDDI2C

AVDD

AGND

GND

VDDQ

GND

VDDQ

GND

VDDQ

SDA

FBIN

VDDQ

FBOUT

GND

VDDQ

SW00506

GND

PIN DESCRIPTION

PINS

SYMBOL

DESCRIPTION

1, 7, 8, 18, 24, 25, 31,

41, 42, 48

GND

Ground

2, 3, 5, 6, 9, 10, 19, 20,

22, 23, 26, 27, 29, 30,

32, 33, 39, 40, 43, 44,

46, 47

Yn, Yn,

FBOUT, FBOUT

Buffered output

copies of input clock,

CLK

4, 11, 21, 28, 34, 38,

VDDQ

2.5 V supply

13, 14, 35, 36

CLK, CLK,

FBIN, FBIN

Differential clock

inputs and feedback

differential clock

inputs

AVDD

Analog power

AGND

Analog ground

SDA

Serial data

SCL

Serial clock

VDDI2C

I2C power

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DRAWING NUMBER

48-Pin Plastic TSSOP

0 to +70

°C

PCK2057DGG

SOT362-1

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