PCK2509SL datasheet(2/10 Pages) PHILIPS

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Philips Semiconductors

Product specification

PCK2509SL

50–150 MHz 1:9 SDRAM clock driver

2000 Dec 01

853–2230 25137

FEATURES

• Phase-Locked Loop Clock distribution for

PC100/PC133 SDRAM applications

• When outputs are disabled, the PLL and feedback output are

disabled, dropping AICC to 100 µA in stand-by mode when input

clock signal is present.

• See PCK2509SA for JEDEC compliant option where PLL remains

locked when outputs are disabled.

• Spread Spectrum clock compatible

• Operating frequency 50 to 150 MHz

• (t

phase error – jitter) at 100 to133 MHz = ±50 ps

• Jitter (peak-peak) at 100 to 133 MHz = ± 80 ps

• Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps

• Pin-to-pin skew < 200 ps

• Available in plastic 24-Pin TSSOP

• Distributes one clock input to one bank of five outputs and one

bank of four outputs

• External Feedback (FBIN) terminal Is used to synchronize the

outputs to the clock input

• On-Chip series damping resistors

• No external RC network required

• Operates at 3.3 V

• Inputs compatible with 2.5 V and 3.3 V ranges

• See page 7 for Characteristic curves.

DESCRIPTION

The PCK2509SL is a high-performance, low-skew, low-jitter,

phase-locked loop (PLL) clock driver. It uses a PLL to precisely

align, in both frequency and phase, the feedback (FBOUT) output to

the clock (CLK) input signal. It is specifically designed for use with

synchronous DRAMs. The PCK2509SL operates at 3.3 V VCC and

is input compatible with both 2.5 V and 3.3 V input voltage ranges. It

also provides integrated series-damping resistors that make it ideal

for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine

low-skew, low-jitter copies of CLK. Output signal duty cycles are

adjusted to 50 percent, independent of the duty cycle at CLK. Each

bank of outputs can be enabled or disabled separately via the

control (1G and 2G) inputs. When the G inputs are high, the outputs

switch in phase and frequency with CLK; when the G inputs are low,

the outputs are disabled to the logic–low state.

Unlike many products containing PLLs, the PCK2509SL does not

require external RC networks. The loop filter for the PLL is included

on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the PCK2509SL requires a

stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required, following power up

and application of a fixed-frequency, fixed-phase signal at CLK, and

following any changes to the PLL reference or feedback signals. The

PLL can be bypassed for test purposes by strapping AVCC to ground.

The PCK2509SL is characterized for operation from 0

°C to +70 °C.

PIN CONFIGURATION

AGND

CLK

AVCC

VCC

2Y0

1Y0

2Y1

GND

1Y1

GND

2Y3

1Y2

2Y2

GND

VCC

FBIN

GND

1Y3

1Y4

VCC

FBOUT

SW00389

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DRAWING NUMBER

24-Pin Plastic TSSOP

0 to +70

°C

PCK2509SLDH

SOT355-1

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