PCK953 datasheet(4/8 Pages) PHILIPS

4 / 8 page

Philips Semiconductors

Product specification

PCK953

50–125 MHz PECL input/CMOS output

3.3 V PLL clock driver

2001 Feb 08

DC CHARACTERISTICS

Tamb = 0 to 70°C; VCC = 3.3 V ±5%

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

VIH

Input HIGH voltage LVCMOS inputs

2.0

—

3.6

VIL

Input LOW voltage LVCMOS inputs

—

0.8

Vp-p

Peak-to-peak input voltage

PECL_CLK

300

—

1000

VCMR

Common mode range

PECL_CLK

Note 1

VCC–1.5

—

VCC–0.6

VOH

Output HIGH voltage

IOH = –20 mA;2

2.4

—

VOL

Output LOW voltage

IOL = 20 mA;2

—

0.5

IIN

Input current

—

±75

µA

CIN

Input capacitance

—

CPD

Power dissipation capacitance

per output

—

ICC

Maximum quiescent supply current

All VCC pins

—

ICCPLL

Maximum PLL supply current

VCCA pin only

—

NOTES:

1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is within

the VCMR range and the input swing lies within the VPP specification.

2. The PCK953 outputs can drive series or parallel terminated 50

Ω (or 50 Ω to VCC/2) transmission lines on the incident edge (see

Applications info section).

PLL INPUT REFERENCE CHARACTERISTICS

Tamb = 0 to 70°C

SYMBOL

PARAMETER

CONDITION

MIN

MAX

UNIT

fref

Reference input frequency

125

MHz

frefDC

Reference input duty cycle

NOTE:

1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.

AC CHARACTERISTICS

Tamb = 0 to 70°C; VCC = 3.3 V ±5%

SYMBOL

PARAMETER

CONDITION

MIN

TYP

MAX

UNIT

tr, tf

Output rise/fall time

0.8 V to 2.0 V

0.30

0.55

0.8

tpw

Output duty cycle

tsk(O)

Output-to–output skews (relative to QFB)

—

100

fVCO

PLL VCO lock range

200

—

500

MHz

fMAX

Maximum output frequency

PLL mode

VCO_SEL = 1

—

100

MHz

PLL mode

VCO_SEL = 0

125

MHz

Bypass mode

225

MHz

tpd(lock)

Input to EXT_FB delay (with PLL locked)

fref = 50 MHz

–75

—

125

tpd(by-

pass)

Input to Q delay

PLL bypassed

5.2

tPLZ-HZ

Output disable time

—

tPZL

Output enable time

—

tjitter

Cycle-to-cycle jitter (peak-to-peak)

—

100

tlock

Maximum PLL lock time

—

0.01

NOTE:

1. X will be targeted for 0 ns, but may vary from target by

±150 ps based on characterization of silicon.

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