AD9912

Preliminary Technical Data

Rev. Pr

B | Page 2 of 3

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

AD9912

TOP VIEW

(Not to Scale)

1

11

10

9

8

7

6

5

4

3

2

16

15

14

13

12

48

38

39

40

41

42

43

44

45

46

47

33

34

35

36

37

AVDD

DVDD_I/O

DVSS

DVDD

S1

S2

N/C

DVSS

DVDD

DVSS

DVDD

DVSS

N/C

AVDD3

N/C

N/C

DAC_RSET

AVDD3

AVDD

AVDD3

AVSS

AVDD

FDBK_IN

N/C

FDBK_INB

AVSS

OUT_CMOS

AVDD3

AVDD

AVSS

OUT

OUTB

Figure 2: 64-Lead LFCSP Pin Configuration

Table 2: Pin Function Descriptions

Pin No.

Input/

Output

Pin

Type

Mnemonic

Description

1

I

Power

DVDD_I/O

3.3V I/O Digital Supply

2, 4, 6, 8

I

Power

DVSS

Digital Ground: Connect to Ground

3, 5, 7

I

Power

DVDD

1.8V Digital Supply

9, 10, 54,

55

I/O

3.3V

CMOS

S1, S2, S3, S4

Configurable startup strapping pins: These pins are configured under program control

(see “Default Power-up Frequency Options for 1 GHz System Clock” on Page 21. After

power-up, these pins become outputs.

11, 19, 23-

26, 29, 30,

36, 42, 45,

53

I

Power

AVDD

Analog Supply: Connect to a nominal 1.8V Supply