| Electronic Components Datasheet Search |
|
TMD27253 Datasheet(PDF) 32 Page - OSRAM GmbH |
|
|
|||||||||||||||||||||||||||||
TMD27253 Datasheet(HTML) 32 Page - OSRAM GmbH |
|
32 / 51 page ![]() Datasheet, Public Page 31 [v2-00] 2023-Feb-22 Document Feedback TMD2725 − Register Description Figure 44: AGAIN Range CFG3 Register (Address 0xAB) Figure 45: CFG3 Register AGAIN[1] AGAIN[0] AGAINMAX AGAINL Overall ALS Gain 00 0 0 ½ 00 0 1 1 01 0 1 4 10 0 1 16 11 0 1 64 11 1 1 128 Addr: 0xAB CFG3 Bit Bit Name Default Access Bit Description 7 INT_READ_CLEAR 0 RW If the Interrupt-Clear-by-Read bit is set, then all flag bits in the STATUS register will be reset whenever the STATUS register is read over I²C. 6:5 Reserved 10 RW Reserved 4SAI 0 RW The Sleep After Interrupt bit is used to place the device into a low power mode upon an interrupt pin assertion. PON SAI INT Oscillator 0X X OFF 10 X ON 11 1 ON 11 0 OFF 3:0 Reserved 1100 RW Reserved |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |