3D3521

MONOLITHIC MANCHESTER

ENCODER

(SERIES 3D3521)

FEATURES

•

All-silicon, low-power CMOS

technology

•

3.3V operation

•

CMOS compatible inputs and

outputs

•

Vapor phase, IR and wave

solderable

•

Auto-insertable (DIP pkg.)

•

Low ground bounce noise

•

Maximum data rate: 50 MBaud

FUNCTIONAL DESCRIPTION

The 3D3521 is a monolithic CMOS Manchester Encoder. The clock

and data, present at the unit input, are combined into a single bi-phase-

level signal. In this encoding mode, a logic one is represented by a

high-to-low transition within the bit cell, while a logic zero is represented

by a low-to-high transition. The unit operating baud rate (in Mbaud) is

equal to the input clock frequency (in MHZ). All pins marked N/C must

be left unconnected.

data

delay



3

PACKAGES

8

7

6

5

1

2

3

4

CLK

RESB

DAT

GND

VDD

N/C

TXB

TX

3D3521M

DIP (.300)

3D3521H

Gull Wing (.300)

3D3521Z

SOIC (.150)

14

13

12

11

10

9

8

1

2

3

4

5

6

7

CLK

N/C

N/C

RESB

DAT

N/C

GND

VDD

N/C

N/C

N/C

N/C

TXB

TX

3D3521

DIP (.300)

3D3521G Gull Wing (.300)

3D3521D SOIC (.150)

PIN DESCRIPTIONS

DAT

Data Input

CLK

Clock Input

RESB Reset

TX

Signal Output

TXB

Inverted Signal Output

VDD

+3.3 Volts

GND

Ground

For mechanical dimensions, click

here.

For package marking details, click

here.

The all-CMOS 3D3521 integrated circuit has been designed as a reliable, economic alternative to hybrid

Manchester Encoders. It is CMOS-compatible and is offered in standard 8-pin and 14-pin auto-insertable

DIPs and space saving surface mount 8-pin and 14-pin SOICs.

Doc #06004

DATA DELAY DEVICES, INC.

1

5/8/2006

3 Mt. Prospect Ave. Clifton, NJ 07013