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MPC8323CVRADDC Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

Part # MPC8323CVRADDC
Description  PowerQUICC??II Pro Integrated Communications Processor Family Hardware Specifications
PDF  80 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8323CVRADDC Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc

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MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
18
Freescale Semiconductor
DUART
7DUART
This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8323E.
7.1
DUART DC Electrical Characteristics
Table 20 provides the DC electrical characteristics for the DUART interface of the MPC8323E.
7.2
DUART AC Electrical Specifications
Table 21 provides the AC timing parameters for the DUART interface of the MPC8323E.
8
Ethernet and MII Management
This section provides the AC and DC electrical characteristics for Ethernet and MII management.
8.1
Ethernet Controller (10/100 Mbps)—MII/RMII Electrical
Characteristics
The electrical characteristics specified here apply to all MII (media independent interface) and RMII
(reduced media independent interface), except MDIO (management data input/output) and MDC
Table 20. DUART DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD + 0.3
V
Low-level input voltage OVDD
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 μAVOH
OVDD – 0.2
V
Low-level output voltage, IOL = 100 μAVOL
—0.2
V
Input current (0 V
≤ VIN ≤ OVDD)1
IIN
—±5
μA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 21. DUART AC Timing Specifications
Parameter
Value
Unit
Notes
Minimum baud rate
256
baud
Maximum baud rate
> 1,000,000
baud
1
Oversample rate
16
2
Notes:
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.



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