P9S12XEP100J1VVLR datasheet(57/1036 Pages) FREESCALE

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Chapter 1 Device Overview MC9S12XE-Family

MC9S12XE-Family Reference Manual Rev. 1.07

Freescale Semiconductor

1.2.3.37

PJ3 / KWJ3 — PORT J I/O Pin 3

PJ2 is a general-purpose input or output pins. It can be conﬁgured as a keypad wakeup input.

1.2.3.38

PJ2 / KWJ2 / CS1 — PORT J I/O Pin 2

PJ2 is a general-purpose input or output pins. It can be conﬁgured as a keypad wakeup input. It can also

be conﬁgured as chip-select output.

1.2.3.39

PJ1 / KWJ1 / TXD2 — PORT J I/O Pin 1

PJ1 is a general-purpose input or output pin. It can be conﬁgured as a keypad wakeup input. It can be

conﬁgured as the transmit pin TXD of the serial communication interface 2 (SCI2).

1.2.3.40

PJ0 / KWJ0 / RXD2 / CS3 — PORT J I/O Pin 0

PJ0 is a general-purpose input or output pin. It can be conﬁgured as a keypad wakeup input. It can be

conﬁgured as the receive pin RXD of the serial communication interface 2 (SCI2).It can also be conﬁgured

as chip-select output 3.

1.2.3.41

PK7 / EWAIT / ROMCTL — Port K I/O Pin 7

PK7 is a general-purpose input or output pin. During MCU emulation modes and normal expanded modes

of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At

the rising edge of RESET, the state of this pin is latched to the ROMON bit. The EWAIT input signal

maintains the external bus access until the external device is ready to capture data (write) or provide data

(read).

The input voltage threshold for PK7 can be conﬁgured to reduced levels, to allow data from an external

3.3-V peripheral to be read by the MCU operating at 5.0 V.

1.2.3.42

PK[6:4] / ADDR[22:20] / ACC[2:0] — Port K I/O Pin [6:4]

PK[6:4] are general-purpose input or output pins. During MCU expanded modes of operation, the

ACC[2:0] signals are used to indicate the access source of the bus cycle. This pins also provide the

expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is

time multiplexed with the high addresses

1.2.3.43

PK[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O Pins [3:0]

PK3-PK0 are general-purpose input or output pins. In MCU expanded modes of operation, these pins

provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information.

1.2.3.44

PL7 / TXD7 — Port L I/O Pin 7

PL7 is a general-purpose input or output pin. It can be conﬁgured as the transmit pin TXD of serial

communication interface 7 (SCI7).

P9S12XEP100J1VVLR Datasheet(PDF) 57 Page - Freescale Semiconductor, Inc

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