PC9S12XEP100J1MVLR datasheet(73/1036 Pages) FREESCALE

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Chapter 1 Device Overview MC9S12XE-Family

MC9S12XE-Family Reference Manual Rev. 1.07

Freescale Semiconductor

1.6.3

Effects of Reset

When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block

descriptions for register reset states.

On each reset, the Flash module executes a reset sequence to load Flash configuration registers and

initialize the buffer RAM EEE partition, if required.

1.6.3.1

Flash Conﬁguration Reset Sequence Phase

On each reset, the Flash module will hold CPU activity while loading Flash module registers from the

Flash memory. If double faults are detected in the reset phase, Flash module protection and security may

be active on leaving reset. This is explained in more detail in the Flash module section.

1.6.3.2

EEE Reset Sequence Phase

During the reset phase the EEE buffer array is loaded with valid data from the D-Flash EEE partition. In

this reset phase CPU activity is held so device accesses to the EEE before the Flash memory controller

reset is completed are stalled.

If conﬁgured for EEE operation (ERPART > 0), all valid EEE records from the D-Flash EEE partition will

be copied to the buffer RAM EEE partition.

1.6.3.3

Reset While Flash Command Active

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The

state of the word being programmed or the sector/block being erased is not guaranteed.

1.6.3.4

I/O Pins

Refer to the PIM block description for reset conﬁgurations of all peripheral module ports.

Vector base + $3E

$1F

ATD0 Compare Interrupt

I bit

ATD0CTL2 (ACMPIE)

Vector base + $3C

$1E

ATD1 Compare Interrupt

I bit

ATD1CTL2 (ACMPIE)

Vector base+ $18

Vector base + $3A

Reserved

Vector base + $16

—

XGATE software error interrupt

None

Vector base + $14

—

MPU Access Error

None

Vector base + $12

—

System Call Interrupt (SYS)

—

None

Vector base + $10

—

Spurious interrupt

—

None

1 16 bits vector address based

2 For detailed description of XGATE channel ID refer to XGATE Block Guide

Table 1-13. Interrupt Vector Locations (Sheet 4 of 4)

Vector Address1

XGATE

Channel ID2

Interrupt Source

CCR

Mask

Local Enable

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