TMS320DM6443 datasheet(13/221 Pages) TI

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2.3.8

ARM Memory Mapping

2.3.9

Peripherals

2.3.10 PLL Controller (PLLC)

TMS320DM6443

Digital Media System-on-Chip

SPRS282E – DECEMBER 2005 – REVISED MARCH 2007

The DM6443 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer.

The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured

trace data.

The ARM memory map is shown in Section 2.5, Memory Map Summary of this document. The ARM has

access to memories shown in the following sections.

2.3.8.1 ARM Internal Memories

The ARM has access to the following ARM internal memories:

• 16KB ARM Internal RAM on TCM interface, logically separated into two 8KB pages to allow

simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data

(D-TCM) to the different memory regions.

• 8KB ARM Internal ROM

2.3.8.2 External Memories

The ARM has access to the following external memories:

• DDR2 Synchronous DRAM

• Asynchronous EMIF / NOR Flash / NAND Flash

• ATA/CF

• Flash card devices:

–

MMC/SD with SDIO

–

SmartMedia

2.3.8.3 DSP Memories

The ARM has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

2.3.8.4 ARM-DSP Integration

DM6443 ARM and DSP integration features are as follows:

• DSP visibility from ARM’s memory map, see Section 2.5, Memory Map Summary, for details

• Boot Modes for DSP - see Device Configurations section, Section 3.3.3, DSP Boot, for details

• ARM control of DSP boot / reset - see Device Configurations section, Section 3.3.2, ARM Boot, for

details

• ARM control of DSP isolation and powerdown / powerup - see Section 3, Device Configurations, for

details

• ARM & DSP Interrupts - see Section 6.7.1, ARM CPU Interrupts, and Section 6.7.2, DSP Interrupts, for

details

The ARM9 has access to all of the peripherals on the DM6443 device.

The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for

configuring DM6443’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following

configuration and control:

• PLL Bypass Mode

• Set PLL multiplier parameters

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