TLC2933A

HIGH PERFORMANCE PHASE LOCKED LOOP

SLES149 − OCTOBER 2005

3

TI.COM

detailed description

VCO oscillation frequency

and the BIAS terminals. The oscillation frequency and range depends on this Resistor value. For the lock

frequency range, refer to the recommended operating conditions. Figure 1 shows the typical frequency

variation and VCO control voltage.

Bias Resistor (RBIAS)

VCO Oscillation Frequency Range

1/2 VDD

VCO Control Voltage (VCO IN)

Figure 1.

Oscillation Frequency

VCO output frequency 1/2 divider

should be used for minimum VCO output jitter.

Table 1.

VCO Output 1/2 Divider Function

SELLECT

VCO OUTPUT

Low

fOSC

High

1/2 fOSC

VCO inhibit function

The VCO has an externally controlled inhibit function which inhibit the VCO output. A high level on the VCO

INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during

the power−down mode as shown in Table 2.

Table 2.

VCO Inhibit Function

VCO INHIBIT

VCO OSCILLATOR

VCO OUT

IDD(VCO)

Low

Active

Active

Normal

High

Stopped

Low level

Power Down

PFD operation

The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase

difference between two frequency inputs supplied to FIN−A and FIN−B as shown in Figure 2. Normally the

reference is supplied to FIN−A and the frequency from the external counter output is fed to FIN−B. For clock

recovery PLL system, other types of phase detectors should be used.