CDC5801A

LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH

PROGRAMMABLE DELAY AND PHASE ALIGNMENT

SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005

2

POST OFFICE BOX 655303

Depending on the selection of the mode terminals (P0:2), the device behaves as a multiplier (by 4, 6, or 8) with

the phase aligner bypassed or as a multiplier or divider with programmable delay and phase aligner functionality.

Through the select terminals (P0:2) user can also bypass the phase aligner and the PLL (test mode) and output

the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could be in a

high impedance state. This device has another unique capability to be able to function with a wide band of

The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all

power up conditions.

The CDC5801A device is characterized for operation over free-air temperatures of −40

°C to 85°C.

functional block diagram

B

A

PLL

Phase

Aligner

VDDPD/2

PLLCLK

CLKOUT

CLKOUTB

REFCLK

φD

LEADLAG

MULT0/DIV0

MULT1/DIV1

2

PWRDWNB

P0

P1

P2

STOPB

Control Logic

Phase Aligner

Bypass MUX

DLYCTRL

Divider

Ratio

VDDREF/2