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DSP56362P Datasheet(PDF) 97 Page - Freescale Semiconductor, Inc |
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DSP56362P Datasheet(HTML) 97 Page - Freescale Semiconductor, Inc |
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97 / 152 page  JTAG Timing DSP56362 Technical Data, Rev. 4 Freescale Semiconductor 3-71 Figure 3-49 Test Clock Input Timing Diagram 508 TMS, TDI data setup time 5.0 — ns 509 TMS, TDI data hold time 25.0 — ns 510 TCK low to TDO data valid 0.0 44.0 ns 511 TCK low to TDO high impedance 0.0 44.0 ns 512 TRST assert time 100.0 — ns 513 TRST setup time to TCK low 40.0 — ns 1 V CC = 3.3 V ± 0.16V; TJ = 0°C to +100°C, CL = 50 pF 2 All timings apply to OnCE module data transfers because it uses the JTAG port as an interface. Table 3-28 JTAG Timing1, 2 (continued) No. Characteristics All Frequencies Unit Min Max TCK (Input) VM VM VIH VIL 501 502 502 503 503 AA0496 |
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