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AD9866BCPRL Datasheet(PDF) 10 Page - Analog Devices

Part # AD9866BCPRL
Description  Broadband Modem Mixed-Signal Front End
PDF  48 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9866BCPRL Datasheet(HTML) 10 Page - Analog Devices

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AD9866
Rev. A | Page 10 of 48
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
33
48
47
46
45
44
43
42
41
40
39
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34
49
64
63
62
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51
50
ADIO11/Tx[5]
ADIO10/Tx[4]
ADIO9/Tx[3]
ADIO8/Tx[2]
ADIO7/Tx[1]
ADIO6/Tx[0]
ADIO5/Rx[5]
ADIO4/Rx[4]
ADIO3/Rx[3]
ADIO2/Rx[2]
ADIO1/Rx[1]
ADIO0/Rx[0]
RXCLK
TXCLK/TXQUIET
TXEN/TXSYNC
RXEN/RXSYNC
AVSS
AVSS
IOUT_N–
IOUT_G–
AVSS
AVDD
REFIO
REFADJ
AVDD
AVSS
RX+
RX–
REFT
AVSS
AVDD
AVSS
AD9866
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Mode1
Description
1
ADIO11
HD
MSB of ADIO Buffer
Tx[5]
FD
MSB of Tx Nibble Input
2 to 5
ADIO10 to 7
HD
Bits 10 to 7 of ADIO Buffer
Tx[4 to 1]
FD
Bits 4 to 1 of Tx Nibble Input
6
ADIO6
HD
Bit 6 of ADIO Buffer
Tx[0]
FD
LSB of Tx Nibble Input
7
ADIO5
HD
Bit 5 of ADIO Buffer
Rx[5]
FD
MSB of Rx Nibble Output
8, 9
ADIO4, 3
HD
Bits 4 to 3 of ADIO Buffer
Rx[4, 3]
FD
Bits 4 to 3 of Rx Nibble Output
10
ADIO2
HD
Bit 2 of ADIO Buffer
Rx[2]
FD
Bit 2 of Rx Nibble Output
11
ADIO1
HD
Bit 1 of ADIO Buffer
Rx[1]
FD
Bit 1 of Rx Nibble Output
12
ADIO0
HD
LSB of ADIO Buffer
Rx[0]
FD
LSB of Rx Nibble Output
13
RXEN
HD
ADIO Buffer Control Input
RXSYNC
FD
Rx Data Synchronization Output
14
TXEN
HD
Tx Path Enable Input
TXSYNC
FD
Tx Data Synchronization Input
15
TXCLK
HD
ADIO Sample Clock Input
TXQUIET
FD
Fast TxDAC/IAMP Power-Down



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