56F8000 datasheet(49/160 Pages) FREESCALE

49 / 160 page

Peripheral Memory-Mapped Registers

56F8025 Data Sheet, Rev. 3

Freescale Semiconductor

Preliminary

Table 4-18 GPIOD Registers Address Map

(GPIOD_BASE = $00 F180)

Address Offset

GPIOD_PUPEN

Pull-up Enable Register

GPIOD_DATA

Data Register

GPIOD_DDIR

Data Direction Register

GPIOD_PEREN

Peripheral Enable Register

GPIOD_IASSRT

Interrupt Assert Register

GPIOD_IEN

Interrupt Enable Register

GPIOD_IEPOL

Interrupt Edge Polarity Register

GPIOD_IPEND

Interrupt Pending Register

GPIOD_IEDGE

Interrupt Edge-Sensitive Register

GPIOD_PPOUTM

Push-Pull Output Mode Control Register

GPIOD_RDATA

Raw Data Input Register

GPIOD_DRIVE

Output Drive Strength Control Register

Table 4-19 Programmable Interval Timer 0 Registers Address Map

(PIT0_BASE = $00 F190)

Address Offset

PIT0_CTRL

Control Register

PIT0_MOD

Modulo Register

PIT0_CNTR

Counter Register

Table 4-20 Programmable Interval Timer 1 Registers Address Map

(PIT1_BASE = $00 F1A0)

Address Offset

PIT1_CTRL

Control Register

PIT1_MOD

Modulo Register

PIT1_CNTR

Counter Register

Table 4-21 Programmable Interval Timer 2 Registers Address Map

(PIT2_BASE = $00 F1B0)

Address Offset

PIT2_CTRL

Control Register

PIT2_MOD

Modulo Register

56F8000 Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc

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