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56F8335 Datasheet(PDF) 138 Page - Freescale Semiconductor, Inc |
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56F8335 Datasheet(HTML) 138 Page - Freescale Semiconductor, Inc |
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138 / 160 page  56F8335 Technical Data, Rev. 5 138 Freescale Semiconductor Preliminary Figure 10-8 Recovery from Stop State Using Asynchronous Interrupt Timing 10.9 Serial Peripheral Interface (SPI) Timing Table 10-17 SPI Timing1 Characteristic Symbol Min Max Unit See Figure Cycle time Master Slave tC 50 50 — — ns ns 10-9, 10-10, 10-11, 10-12 Enable lead time Master Slave tELD — 25 — — ns ns 10-12 Enable lag time Master Slave tELG — 100 — — ns ns 10-12 Clock (SCK) high time Master Slave tCH 17.6 25 — — ns ns 10-9, 10-10, 10-11, 10-12 Clock (SCK) low time Master Slave tCL 24.1 25 — — ns ns 10-12 Data set up time required for inputs Master Slave tDS 20 0 — — ns ns 10-9, 10-10, 10-11, 10-12 Data hold time required for inputs Master Slave tDH 0 2 — — ns ns 10-9, 10-10, 10-11, 10-12 Access time (time to data active from high-impedance state) Slave tA 4.8 15 ns 10-12 Disable time (hold time to high-impedance state) Slave tD 3.7 15.2 ns 10-12 Data Valid for outputs Master Slave (after enable edge) tDV — — 4.5 20.4 ns ns 10-9, 10-10, 10-11, 10-12 Not IRQA Interrupt Vector tIW IRQA tIF A0–A15 First Instruction Fetch |
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