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PR31100ABC Datasheet(PDF) 14 Page - NXP Semiconductors |
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PR31100ABC Datasheet(HTML) 14 Page - NXP Semiconductors |
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14 / 26 page  Philips Semiconductors Preliminary specification MIPS PR31100 Highly integrated embedded processor 1996 Aug 07 14 MEMORY INTERFACE Tamb = 0 to +70°C, VDD = 3.3 ± 0.3V, External Capacitance = 40pF ITEM PARAMETER RISING/FALLING LIMITS UNIT ITEM PARAMETER RISING/FALLING MIN MAX UNIT 1 DCLKOUT high time – 5 – ns 2 DCLKOUT low time – 5 – ns 3 DCLKOUT period – 12.5 – ns 4 Delay DCLKOUT to ALE Rising – 4 ns 4 Delay DCLKOUT to ALE Falling – 3 ns 4 Delay DCLKOUT to A[12:0] – – 8 ns 4 Delay DCLKOUT to D[31:16] – – 8 ns 4 Delay DCLKOUT to D[15:0] – 1.5 8 ns 4 Delay DCLKOUT to /CS3–0 Rising – 10 ns 4 Delay DCLKOUT to /CS3–0 Falling – 10 ns 4 Delay DCLKOUT to /RD Risng – 8 ns 4 Delay DCLKOUT to /RD Falling – 7 ns 4 Delay DCLKOUT to /WE Rising – 5 ns 4 Delay DCLKOUT to /WE Falling – 4 ns 4 Delay DCLKOUT to /SAS3–0 Rising – 1.5 ns 4 Delay DCLKOUT to /SAS3–0 Falling – 1.5 ns 4 Delay DCLKOUT to /CARDxCSx Rising – 9 ns 4 Delay DCLKOUT to /CARDxCSx Falling – 8 ns 4 Delay DCLKOUT to /CARDDIR Rising – 12 ns 4 Delay DCLKOUT to /CARDDIR Falling – 11 ns 4 Delay DCLKOUT to /CARDREG Rising – 9 ns 4 Delay DCLKOUT to /CARDREG Falling – 10 ns 4 Delay DCLKOUT to /IORD Rising – 10 ns 4 Delay DCLKOUT to /IORD Falling – 9 ns 4 Delay DCLKOUT to /IOWR Rising – 9 ns 4 Delay DCLKOUT to /IOWR Falling – 9 ns 4 Delay DCLKOUT to /RAS0 Rising – 6 ns 4 Delay DCLKOUT to /RAS0 Falling – 6 ns 4 Delay DCLKOUT to /RAS1 Rising 1.5 8 ns 4 Delay DCLKOUT to /RAS1 Falling 1.5 9 ns 4 Delay DCLKOUT to DQMH/L Rising 1.5 8 ns 4 Delay DCLKOUT to DQMH/L Falling 1.5 9 ns 4 Delay DCLKOUT to /DCS0 Rising 1.5 7 ns 4 Delay DCLKOUT to /DCS0 Falling 1.5 6 ns 4 Delay DCLKOUT to DCKE Rising 1.5 8 ns 4 Delay DCLKOUT to DCKE Falling 1.5 8 ns 4 Delay DCLKOUT to /MCS3–0 Rising – 10 ns 4 Delay DCLKOUT to /MCS3–0 Falling – 10 ns 5 D[31:16] to DCLKIN Setup time – 2 – ns 6 D[31:16] to DCLKIN Hold time – 1 – ns 5 D[15:0] to DCLKIN Setup time – 1 – ns 6 D[15:0] to DCLKIN Hold time – 1.5 – ns 7 DCLKOUT to DCLKIN Board Delay time – 0 3 ns |
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