DATA SHEET

• SC SERIES: MIS CHIP CAPACITORS

Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com

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May 25, 2011 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200136G

Table 1. MIS Capacitors Absolute Maximum Ratings

Parameter

Symbol

Minimum

Typical

Maximum

Units

Dielectric withstand voltage

100

V

Operating temperature

TOP

–65

+200

°C

Storage temperature

TSTG

–65

+200

°C

Note: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other

parameters set at or below their nominal value.

CAUTION: Although this device is designed to be as robust as possible, Electrostatic Discharge (ESD) can damage this device. This device

must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body

or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times.

Table 2. MIS Chip Capacitors Electrical Specifications (Note 1)

Parameter

Symbol

Test Condition

Min

Typical

Max

Units

Capacitance

0.8

1000

pF

Temperature coefficient

50

ppm/°C

Capacitance tolerance

–20

+20

%

Operating temperature

TOP

–65

+200

°C

Dielectric withstand voltage

100

V

Insulation resistance

105

M

Ω

Leakage current

<1

nA

Note 1: Performance is guaranteed only under the conditions listed in this Table.

Electrical and Mechanical Specifications

The absolute maximum ratings of the MIS chip capacitors are

provided in Table 1. Electrical specifications are provided in

Table 2.

A graph of typical insertion loss versus frequency is shown in

Figure 1. This data is taken from an actual test circuit with series

mounted beam-lead or chip capacitors on a 50

Ω microstrip

transmission line. The apparent higher loss at lower frequencies

on the lower capacitance units is strictly due to the capacitive

reactance of the capacitor.

Table 3 provides a list of the available MIS chip capacitors (by part

number) and the capacitance and chip dimensions for each one.

Performance

Tests on typical MIS capacitors at the L and S bands show

insertion loss to be 1/2 to 1/3 that of equivalent ceramic type

capacitors, without any of the associated resonance problems.

Power tests indicate that the only limitation is the actual

breakdown voltage of the device.

Figure 2 illustrates the use of MIS capacitors in a typical Single-

Pole, Double-Throw (SPDT) circuit.

Package Dimensions

Figure 3 provides a visual representation of the capacitor chip

sizes and part markings.