MPC862P datasheet(40/88 Pages) FREESCALE

40 / 88 page

MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Bus Signal Timing

Table 10 shows the PCMCIA port timing for the MPC862/857T/857DSL.

Figure 29 provides the PCMCIA output port timing for the MPC862/857T/857DSL.

Figure 29. PCMCIA Output Port Timing

Figure 30 provides the PCMCIA output port timing for the MPC862/857T/857DSL.

Figure 30. PCMCIA Input Port Timing

Table 10. PCMCIA Port Timing

Num

Characteristic

33 MHz

40 MHz

50 MHz

66 MHz

Unit

Min

Max

Min

Max

Min

Max

Min

Max

P57

CLKOUT to OPx Valid (MAX = 0.00 x

B1 + 19.00)

—

19.00

—

19.00

—

19.00

—

19.00

P58

HRESET negated to OPx drive 1

(MIN = 0.75 x B1 + 3.00)

OP2 and OP3 only.

25.70

—

21.70

—

18.00

—

14.40

—

P59

IP_Xx valid to CLKOUT rising edge

(MIN = 0.00 x B1 + 5.00)

5.00

—

5.00

—

5.00

—

5.00

—

P60

CLKOUT rising edge to IP_Xx invalid

(MIN = 0.00 x B1 + 1.00)

1.00

—

1.00

—

1.00

—

1.00

—

CLKOUT

HRESET

Output

Signals

OP2, OP3

P57

P58

CLKOUT

Input

Signals

P59

P60

MPC862P Datasheet(PDF) 40 Page - Freescale Semiconductor, Inc

MPC862P Datasheet(HTML) 40 Page - Freescale Semiconductor, Inc

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