MPC880 datasheet(61/92 Pages) FREESCALE

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MPC885/MPC880 Hardware Specifications, Rev. 3

Freescale Semiconductor

CPM Electrical Characteristics

Figure 60. HDLC Bus Timing Diagram

12.8 Ethernet Electrical Specifications

Table 24 provides the Ethernet timings as shown in Figure 61 to Figure 63.

Table 24. Ethernet Timing

Num

Characteristic

All Frequencies

Unit

Min

Max

120

CLSN width high

—

121

RCLK1 rise/fall time

—

122

RCLK1 width low

—

123

RCLK1 clock period 1

120

124

RXD1 setup time

—

125

RXD1 hold time

—

126

RENA active delay (from RCLK1 rising edge of the last data bit)

—

127

RENA width low

100

—

128

TCLK1 rise/fall time

—

129

TCLK1 width low

—

130

TCLK1 clock period1

101

131

TXD1 active delay (from TCLK1 rising edge)

—

132

TXD1 inactive delay (from TCLK1 rising edge)

6.5

133

TENA active delay (from TCLK1 rising edge)

TCLK1

CTS1

(Echo Input)

102

100

104

TxD1

(Output)

102

101

RTS1

(Output)

103

104

107

105

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