MPC5553_07 datasheet(12/66 Pages) FREESCALE

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MPC5553 Microcontroller Data Sheet, Rev. 2.0

Electrical Characteristics

Freescale Semiconductor

Table 8 gives the pin state for the sequence cases for all pins with pad type pad_mh (medium type) and

pad_sh (slow type).

3.7.1

Input Value of Pins During POR Dependent on VDD33

When powering up the device, VDD33 must not lag the latest VDDSYN or RESET power pin (VDDEH6) by

more than the VDD33 lag specification listed in Table 6, spec 8. This avoids accidentally selecting the

bypass clock mode because the internal versions of PLLCFG[0:1] and RSTCFG are not powered and

therefore cannot read the default state when POR negates. VDD33 can lag VDDSYN or the RESET power

pin (VDDEH6), but cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification

applies during power up only. VDD33 has no lead or lag requirements when powering down.

3.7.2

Power-Up Sequence (VRC33 Grounded)

The 1.5 V VDD power supply must rise to 1.35 V before the 3.3 V VDDSYN power supply and the RESET

power supply rises above 2.0 V. This ensures that digital logic in the PLL for the 1.5 V power supply does

not begin to operate below the specified operation range lower limit of 1.35 V. Because the internal 1.5 V

POR is disabled, the internal 3.3 V POR or the RESET power POR must hold the device in reset. Since

they can negate as low as 2.0 V, VDD must be within specification before the 3.3 V POR and the RESET

POR negate.

Figure 2. Power-Up Sequence (VRC33 Grounded)

Table 8. Power Sequence Pin Status for Medium / Slow Pads

VDDEH

VDD

POR

Pin Status for Medium and Slow Pad Output Driver

pad_mh (medium) pad_sh (slow)

Low

—

Asserted

Low

VDDEH

Low

Asserted

High impedance (Hi-Z)

VDDEH

VDD

Asserted

Hi-Z

VDDEH

VDD

Negated

Functional

VDDSYN and RESET Power

VDD

2.0 V

1.35 V

VDD must reach 1.35 V before VDDSYN and the RESET power reach 2.0 V

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