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SA5222 Datasheet(PDF) 2 Page - NXP Semiconductors

Part # SA5222
Description  Low-power FDDI transimpedance amplifier
PDF  8 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SA5222 Datasheet(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
SA5222
Low-power FDDI transimpedance amplifier
1995 Apr 26
2
DC ELECTRICAL CHARACTERISTICS
Typical data and Min and Max limits apply at TA = 25°C, and VCC1 = VCC2 = +5V, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
SA5222
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
VIN
Input bias voltage
1.3
1.55
1.8
V
VO±
Output bias voltage
2.9
3.2
3.5
V
VOS
Output offset voltage
0
±100
mV
ICC
Supply current
6
9
12
mA
IOMAX
Output sink/source current
1.5
2
mA
IIN
Input current (2% linearity)
Test circuit 5, Procedure 2
±60
±90
µA
IINMAX
Maximum input current overload threshold
Test circuit 5, Procedure 4
±80
±115
µA
VOMAX
Maximum differential output voltage swing
RL = ∞, Test Circuit 5, Procedure 3
3.6
VP-P
AC ELECTRICAL CHARACTERISTICS
Typical data and Min and Max limits apply at TA = 25°C and VCC1 = VCC2 =+5V, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
SA5222
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
RT
Transresistance (differential output)
DC tested, RL = ∞, Test Circuit 5,
Procedure 1
13.3
16.6
19.9
k
Ω
RO
Output resistance
(differential output)
DC tested
30
60
90
Ω
RT
Transresistance
(single-ended output)
DC tested, RL = ∞
6.65
8.3
9.95
k
Ω
RO
Output resistance
(single-ended output)
DC tested
15
30
45
Ω
f3dB
Bandwidth (-3dB)1
Test Circuit 1
110
140
MHz
RIN
Input resistance
150
Ω
CIN
Input capacitance2
1
pF
∆R/∆V
Transresistance power supply sensitivity
VCC1 = VCC2 = 5 ±0.5V
1.0
%/V
∆R/∆T
Transresistance ambient temperature sensi-
tivity
∆TA = TA MAX - TA MIN
0.07
%/oC
IIN
RMS noise current spectral density (referred
to input)
Test Circuit 2, f = 10MHz
2.0
pA
Hz
IT
Integrated RMS noise current over the band-
width (referred to input)
Test circuit 2,
∆f = 50MHz
15
nA
IT
CS = 0pF
∆f = 100MHz
25
nA
IT
∆f = 150MHz
36
nA
IT
CS = 1pF
∆f = 50MHz
17
nA
∆f = 100MHz
35
∆f = 150MHz
55
PSRR
Power supply rejection ratio
DC Tested,
∆VCC = ±0.5V
–55
dB
PSRR
Power supply rejection ratio3
f = 1.0MHz, Test Circuit 3
–34
dB
IINMAX
Maximum input amplitude for output duty
cycle of 50
±5%4
Test circuit 4
±120
µA
tr, tf
Rise and fall times
10 – 90%
2.2
ns
tD
Group delay
f = 10MHz
2.2
ns
NOTES:
1. Bandwidth is tested into 50
Ω load. Bandwidth into 1kΩ load is approximately 165MHz.
2. Does not include Miller-multiplied capacitance of input device.
3. PSRR is output referenced and is circuit board layout dependent at higher frequencies. For best performance use a RF filter in VCC line.
4. Monitored in production via linearity and over load tests.



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