Philips Semiconductors

Objective specification

SA9024

900 MHz transmit modulator and 1.3 GHz

fractional–N synthesizer

1997 Aug 01

15

Data format

Format of programmed data

LAST IN

MSB

SERIAL PROGRAMMING FORMAT

FIRST IN LSB

p23

p22

p21

p20

../..

../..

p1

p0

A word, length 24 bits

Last in

MSB

LSB

First IN

Address

fmod

Fractional–N

Main Divider ratio– Nmain

Spare

0

0

Fmod

NF2

NF1

NF0

N15

N14

N13

N12

N11

N10

N9

N8

N7

N6

N5

N4

N3

N2

N1

N0

sk1

sk2

Default:

0

0

1

0

0

0

1

0

0

0

1

0

0

0

1

1

0

0

0

0

0

0

A word select

Fixed to 00.

Fractional Modulus select

FM 0=modulo 8, 1=modulo 5.

Fractional–N Increment

NF2..0 Fractional N Increment values 000 to 111.

N–Divider

N0..N15, Main divider values 512 to 65535 allowed for divider ratio.

B word, length 24 bits

ADDRESS

REFERENCE DIVIDER NREF

RSM

RSA

FRACTIONAL COMPENSATION DAC

0

1

R9

R8

R7

R6

R5

R4

R3

R2

R1

R0

RSM

1

RSM

0

RSA

1

RSA

0

Fdac

7

Fdac

6

Fdac

5

Fdac

4

Fdac

3

Fdac

2

Fdac

1

Fdac

0

Default:

0

0

0

1

0

1

0

0

0

1

0

0

0

0

x

x

x

x

x

x

x

x

B word select

Fixed to 01

R–Divider

R0..R9, Reference divider values 4 to 1023 allowed for divider ration.

Charge pump current

Ratio

CP1, CP0: Charge pump current ratio, see table of charge pump currents.

Main comparison

select

RSM

Comparison divider select for main phase detector.

Aux comparison select

RSA

Comparison divider select for auxiliary phase detector.

Fractional

Compensation

Fdac7..0, Fractional compensation charge pump current DAC, values 0 to 255. FDAC = 77 for best op MOD8.

C word, length 24 bits

ADDRESS

AUXILIARY DIVIDER NAUX

CP

LOCK

PD

SPARE

1

0

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

CP1

CP0

LD1

LD0

PD1

PD2

PD3

LOD

Default

0

0

0

0

0

1

1

1

0

0

1

0

1

0

1

1

0

0

0

0

C word select

Fixed to 10

A–Divider

A0..A13, Auxiliary divider values 128 to 16384 allowed for divider ratio.

Charge pump current Ratio

CP1, CP0: Charge pump current ratio, see table fo charge pump currents.

Lock detect output

LD1 LD0

0 0

Combined main, aux. & offset loop lock detect signal present at the LOCK pin.

0 1

Combined main and aux. lock detect signal present at the LOCK pin.

1 0

Main lock detect signal present at the LOCK pin.

1 1

Auxiliary loop lock detect signal present at the LOCK pin.

When a section is in power down mode, the lock indicator for that section is high.

Power down

PD1=1: power to N–divider, reference divider, main charge pumps, PD1=0 to power down.

PD2=1: power to Aux divider, reference divider, Aux charge pump, PD2=0 to power down.