NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third

party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not

assume any legal responsibility for any said applications.

MP8102 Rev. 0.94

www.MonolithicPower.com

9

9/27/2006

MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.

© 2006 MPS. All Rights Reserved.

APPLICATION INFORMATION

Power Supply Bypassing

Regular supply bypassing techniques are

recommended. A 10µF capacitor in parallel with

a 0.1µF capacitor on both the positive and

negative supplies is ideal. For the best

performance, all bypassing capacitors should

be located as close to the op amp as possible

and all capacitors should be low ESL

(Equivalent Series Inductance) and low ESR

(Equivalent Series Resistance). Surface mount

ceramic capacitors are ideal.

PACKAGE INFORMATION

TSOT23-5

0.30

0.50

SEATING PLANE

0.95 BSC

0.84

0.90

1.00 MAX

0.00

0.10

TOP VIEW

FRONT VIEW

SIDE VIEW

RECOMMENDED LAND PATTERN

2.80

3.00

1.50

1.70

2.60

3.00

1

3

4

5

0.09

0.20

NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,

PROTRUSION OR GATE BURR.

3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH

OR PROTRUSION.

4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)

SHALL BE 0.10 MILLIMETERS MAX.

5) DRAWING CONFORMS TO JEDEC MO-193, VARIATION AA.

6) DRAWING IS NOT TO SCALE.

0.30

0.50

0.25 BSC

GAUGE PLANE

2.60

TYP

1.20

TYP

0.95

BSC

0.60

TYP

SEE DETAIL "A"

DETAIL A