SAB9079 datasheet(7/48 Pages) PHILIPS

7 / 48 page

2000 Jan 13

Philips Semiconductors

Preliminary speciﬁcation

Multistandard Picture-In-Picture (PIP)

controller

SAB9079HS

AD5

memory address output bit 5 (CMOS levels)

AD4

memory address output bit 4 (CMOS levels)

n.c.

−

not used in application

VDDD(C4)

digital supply voltage 4 for core (3.3 V); note 3

VSSD(C4)

digital ground 4 for core; note 4

VSSD(C5)

digital ground 5 for core; note 4

VDDD(C5)

digital supply voltage 5 for core (3.3 V); note 3

VDDD(P5)

digital supply voltage 5 for periphery (5.0 V); note 2

VSSD(P5)

digital ground 5 for periphery; note 1

VDDA(SH)

supply of sub HSYNC input (5.0 V)

VSSA(SP)

analog ground for sub channel PLL

VDDA(SP)

analog supply voltage for sub channel PLL (3.3 V)

SHSYNC

horizontal sync input for sub channel (CMOS levels with hysteresis)

SVSYNC

vertical sync input for sub channel (CMOS levels with hysteresis)

TSCLK

test clock input for sub (CMOS levels)

TSMSB

test sub MSB output for PLL counter (CMOS levels)

TSEXT

set sub PLL input for external mode (CMOS levels)

VDDA(SA)

analog supply voltage for sub channel ADCs (3.3 V)

VSSA(SA)

100

analog ground for sub channel ADCs

101

analog V input of sub channel

VDDA(SF)

102

analog supply voltage for sub channel frontend (3.3 V)

103

analog U input of sub channel

Vbias(SA)

104

I/O

analog bias reference input for sub channel ADCs

105

analog Y* input of sub channel

Vref(B)(SA)

106

I/O

analog bottom reference for sub channel ADCs

Vref(T)(SA)

107

I/O

analog top reference for sub channel ADCs

VSSD(C6)

108

digital ground 6 for core; note 4

VDDD(C6)

109

digital supply voltage 6 for core (3.3 V); note 3

TCBC

110

test control block clock input (CMOS levels)

TCBD

111

test control block data input (CMOS levels)

TCBR

112

test control block reset input (CMOS levels)

VDDD(P)

113

digital supply voltage for periphery (5.0 V); note 5

114

address select pin input (I2C-bus) (CMOS levels)

SDA

115

I/O

serial input data/ACK output (I2C-bus) (CMOS input levels)

SCL

116

serial clock input (I2C-bus) (CMOS levels)

POR

117

power-on reset input (CMOS levels with hysteresis and pull-up resistor to VDD)

118

test control input (CMOS levels)

TM1

119

I/O

test mode input/output (CMOS levels with hysteresis and pull-up resistor to VDD)

TM2

120

I/O

test mode input/output (CMOS levels with hysteresis and pull-up resistor to VDD)

TM0

121

test mode input (CMOS levels)

VDDD(C7)

122

digital supply voltage 7 for core (3.3 V); note 3

SYMBOL

I/O

DESCRIPTION

SAB9079 Datasheet(PDF) 7 Page - NXP Semiconductors

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