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MGL582

73

88

93

44

43

45

46

47

SCL

74

SDA

T7

T6

TCLK

TM

TCBC

TCBD

TCBR

75

POR

TEST

CONTROL

PKOFF

69

FBL

68

DAC AND BUFFER

DY

8

DV

10

DU

12

Vbias(DA)

9

Vref(T)(DA)

11

Vref(B)(DA)

13

SHSYNC

87

SVSYNC

72

SU

79

SV

81

SY

Vbias(SA)

Vref(T)(SA)

Vref(B)(SA)

83

84

82

80

DHSYNC

94

DVSYNC

70

MU

2

MY

98

MV

Vbias(MA)

Vref(T)(MA)

Vref(B)(MA)

100

97

99

1

PLL AND CLOCK

GENERATOR

DCLK

71

T5 to T0

32 to 37

TC

38

PLL AND CLOCK

GENERATOR

CLAMP AND ADC

CLAMP AND ADC

LINE MEMORY

INTERNAL DRAM

DISPLAY

CONTROL

HORIZONTAL

AND

VERTICAL

FILTER

HORIZONTAL

FILTER

89

34

90

91

92

95

21 to 29, 31,

52 to 60

96

VDDA(MF)

VSSA(MA)

56

VDDA(MA)

VDDA(DA)

714

VSSA(DA)

VDDD(DA)

15

16

VSSD(DA)

VSSD(P1)

17

20

VDDD(P1)

VDDD(RP)

39

40

VDDD(RL)

VSSD(RL)

41

42

VSSD(RM)

VDDD(RM)

61

64

VSSD(RP)

VDDD(P2)

65

66

VSSD(P2)

VSSD(D)

67

76

VDDD(D)

VDDA(SA)

77

78

VSSA(SA)

VDDA(SF)

85

86

VSSD(SA)

VDDD(SA)

SAB9082

VSSD(MA)

VDDD(MA)

n.c.

VDDA(DP)

VSSA(DP)

VSSA(SP)

VDDA(SP)

CONTROL

6

19

VSSD(T1)

and

VSSD(T2)

VSSD(T4)

to

VSSD(T7)

VSSD(T8)

and

VSSD(T9)

18, 19

48 to 51

62, 63

VSSD(T3)

30

4

2

Fig.1 Block diagram.