Philips Semiconductors

Product specification

SC26C562

CMOS dual universal serial communications controller

(CDUSCC)

1998 Sep 04

8

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

Min

Typ

Max

UNIT

Input low voltage:

All except X1/CLK

0.8

V

X1/CLK

0.8

V

Input high voltage except X1/CLK

0 to 70

_C

2.0

V

–40 to +85

_C

2.3

V

X1/CLK

V

Output low voltage:

V

IRQN

0.5

V

Output high voltage:

0.5

(Except open drain outputs)

V

–150

0.0

µA

–150

150

µA

X2 short circuit current

–15

+15

mA

mA

Input low current

–15

RESETN, TxDAKN, RxDAKN

–15

–0.5

µA

Input leakage current

–40 to +85

_C

–1

–10

+1

+10

µA

Output off current high, 3-State data bus

–40 to +85

_C

+1

+10

µA

Output off current low, 3-State data bus

–40 to +85

_C

–1

–10

µA

Open drain output low current in off

state:

EOPN, RDYN

–15

–0.5

µA

IRQN

–1

µA

Open drain output high current in off

state:

EOPN, IRQN, RDYN

–1

1

µA

Power supply current

(see Figure 19 for graphs)

0 to 70

_C

–40 to +85

_C

25

80

95

mA

10

pF

15

pF

20

pF

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not

implied.

2. Clock may be stopped (DC) for testing purposes, or when CDUSCC is in non-operational modes.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static

charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

4. Parameters are valid over specified temperature range.

5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transi-

tion time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V. All time measurements are referenced at input voltages of

0.2V and 3.0V and output voltages of 0.8V and 2.0V, as appropriate.

6. See Figure 20 for test conditions for outputs.

7. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from

midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true

switching has occurred.

8. Execution of the valid command (after it is latched) requires 3 rising edges of X1 (see Figure 15).

9. These values were not explicitly tested; they are guaranteed by design and characterization data.

10. X1/CLK and X2 are not tested with a crystal installed.

11. X1/CLK frequency must be at least the faster of the receiver or transmitter serial data rate.

12. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CSN as the ‘strobing’ input. CSN

and RDN (also CSN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated

first terminates the cycle.