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S71PL129JC0 Datasheet(PDF) 140 Page - SPANSION |
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S71PL129JC0 Datasheet(HTML) 140 Page - SPANSION |
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140 / 153 page  138 S71PL129JC0/S71PL129JB0/S71PL129JA0 S71PL129Jxx_00_A8 October 28, 2005 Advance Info rmation AC Characteristics Write Operation Notes: 1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system operation, please contact local Spansion representative for the relaxation of 1µs limitation. 2. Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR). 3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last. 4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever occurs last. 5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever occurs first. 6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first. 7. tWPH minimum is absolute minimum value for device to detect High level. And it is defined at minimum VIH level. 8. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. 9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data bus is in High-Z. Parameter Symbol 16M 32M 64M Unit Notes Min. Max. Min. Max. Min. Max. Write Cycle Time tWC 70 1000 65 1000 65 1000 ns 1,2 Address Setup Time tAS 0—0—0— ns 3 CE1# Write Pulse Width tCW 45 — 40 — 40 — ns 3 WE# Write Pulse Width tWP 45 — 40 — 40 — ns 3 LB#/UB# Write Pulse Width tBW 45 — 40 — 40 — ns 3 LB#/UB# Byte Mask Setup Time tBS -5 — –5 — –5 — ns 4 LB#/UB# Byte Mask Hold Time tBH -5 — –5 — –5 — ns 5 Write Recovery Time tWR 0—0—0— ns 6 CE1# High Pulse Width tCP 10 — 12 — 12 — ns WE# High Pulse Width tWHP 7.5 1000 7.5 1000 7.5 1000 ns 7 LB#/UB# High Pulse Width tBHP 10 1000 12 1000 12 1000 ns Data Setup Time tDS 15 — 12 — 12 — ns Data Hold Time tDH 0—0—0— ns OE# High to CE1# Low Setup Time for Write tOHCL -5 — –5 — –5 — ns 8 OE# High to Address Setup Time for Write tOES 0—0—0— ns 9 LB# and UB# Write Pulse Overlap tBWO 30 — 30 — 30 — ns |
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