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SCN2681 Datasheet(PDF) 18 Page - NXP Semiconductors |
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SCN2681 Datasheet(HTML) 18 Page - NXP Semiconductors |
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18 / 30 page ![]() Philips Semiconductors Product specification SCN2681 Dual asynchronous receiver/transmitter (DUART) 1998 Sep 04 18 Table 3. Bit Rate Generator Characteristics Crystal or Clock = 3.6864MHz NORMAL RATE (BAUD) ACTUAL 16x CLOCK (kHz) ERROR (%) 50 0.8 0 75 1.2 0 110 1.759 -0.069 134.5 2.153 0.059 150 2.4 0 200 3.2 0 300 4.8 0 600 9.6 0 1050 16.756 -0.260 1200 19.2 0 1800 28.8 0 2000 32.056 0.175 2400 38.4 0 4800 76.8 0 7200 115.2 0 9600 153.6 0 14.4K 230.4 0 19.2k 307.2 0 28.8K 460.8 0 38.4k 614.4 0 57.6K 921.6 0 115.2K 1843.2K 0 NOTE: Duty cycle of 16x clock is 50% ± 1%. Asynchronous UART communications can tolerate frequency error of 4.1% to 6.7% in a “clean” communications channel. The percent of error changes as the character length changes. The above percentages range from 5 bits not parity to 8 bits with parity and one stop bit. The error with 8 bits no parity and one stop bit is 4.6%. If a stop bit length of 9/16 is used, the error tolerance will approach 0 due to a variable error of up to 1/16 bit time in receiver clock phase alignment to the start bit. Table 4. ACR 6:4 Field Definition ACR 6:4 MODE CLOCK SOURCE 000 Counter External (IP2) 001 Counter TxCA – 1x clock of Channel A transmitter 010 Counter TxCB – 1x clock of Channel B transmitter 011 Counter Crystal or external clock (x1/CLK) divided by 16 100 Timer (square wave) External (IP2) 101 Timer (square wave) External (IP2) divided by 16 110 Timer (square wave) Crystal or external clock (x1/CLK) 111 Timer (square wave) Crystal or external clock (x1/CLK) divided by 16 NOTE: Timer mode generates a squarewave. |
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