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APPLICATION INFORMATION

10

0.1

1M

Data Rate – Hz

1

100k

10M

100M

100

1000

5% Jitter

30% Jitter

24 AWG UTP 96

Ω (PVC Dielectric)

FAIL SAFE

Rt = 100

Ω (Typ)

300 k

Ω

300 k

Ω

A

B

Y

SN65LVDM176

SLLS320D – DECEMBER 1998 – REVISED JULY 2000

The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground

differences are less than 1 V with a low common-mode output and balanced interface for very low noise

emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL

speeds without the power and dual supply requirements.

Figure 17. Data Transmission Distance Versus Rate

One of the most common problems with differential signaling applications is how the system responds when no

differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that

its output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV and

within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles the

open-input circuit situation, however.

Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be

when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver

feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the

output to a high-level regardless of the differential input voltage.

Figure 18. Open-Circuit Fail Safe of the LVDS Receiver

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