LTC2607IDE datasheet(10/20 Pages) LINER

10 / 20 page

LTC2607/LTC2617/LTC2627

26071727f

PIN FUNCTIONS

CA0 (Pin 1): Chip Address Bit 0. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (Table 1).

CA1 (Pin 2): Chip Address Bit 1. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (Table 1).

LDAC (Pin 3): Asynchronous DAC Update. A falling edge

of this input after four bytes have been written into the part

immediately updates the DAC register with the contents of

the input register. A low on this input without a complete

32-bit (four bytes including the slave address) data write

transfer to the part wakes up sleeping DACs without

updating the DAC output. Software power-down is dis-

abled when LDAC is low. LDAC is disabled when tied high.

SCL (Pin 4): Serial Clock Input Pin. Data is shifted into the

SDA pin at the rising edges of the clock. This high

impedance pin requires a pull-up resistor or current source

to VCC.

SDA (Pin 5): Serial Data Bidirectional Pin. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This

pin is high impedance while data is shifted in and an open-

drain N-channel output during acknowledgment. Requires

a pull-up resistor or current source to VCC.

CA2 (Pin 6): Chip Address Bit 2. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (Table 1).

VOUTB (Pin 7): DAC Analog Voltage Output. The output

range is VREFLO to VREF.

VCC (Pin 8): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

REF (Pin 9): Reference Voltage Input. The input range

is VREFLO ≤ VREF ≤ VCC.

GND (Pin 10): Analog Ground.

REFLO (Pin 11): Reference Low. The voltage at this pin

sets the zero scale (ZS) voltage of all DACs. The VREFLO pin

can be used at voltages up to 1V for VCC = 5V, or 100mV

for VCC = 3V.

VOUTA (Pin 12): DAC Analog Voltage Output. The output

range is VREFLO to VREF.

Exposed Pad (Pin 13): Ground. Must be soldered to

PCB ground.

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