this rise is seen in Figure 3 as ε, and its duration depends on the pull-up resistor (RPUP) used and the capacitance of the

1-Wire network attached. The voltage VILMAX is relevant for the DS28E83 when determining a logical level, not triggering

any events.

Figure 3 shows the initialization sequence required to begin any communication with the DS28E83. A reset pulse followed

by a presence pulse indicates that the DS28E83 is ready to receive data, given the correct ROM and device function

command. If the bus controller uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to

compensate for the edge. A tRSTL duration of 480μs or longer exits the overdrive mode, returning the device to standard

speed. If the DS28E83 is in overdrive mode and tRSTL is no longer than 80μs, the device remains in overdrive mode. If

the device is in overdrive mode and tRSTL is between 80μs and 480μs, the device resets, but the communication speed

is undetermined.

After the bus controller has released the line, it goes into receive mode. Now the 1-Wire bus is pulled to VPUP through

the pull-up resistor or, in the case of a special driver chip, through the active circuitry. When the threshold VTH is crossed,

the DS28E83 waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To detect a presence

pulse, the controller must test the logical state of the 1-Wire line at tMSP.

The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is expired,

the DS28E83 is ready for data communication. In a mixed population network, tRSTH should be extended to minimum

480μs at standard speed and 48μs at overdrive speed to accommodate other 1-Wire devices.

tRSTL

tPDH

tPDL

tREC

tRSTH

VPUP

VIHCONTROLLER

VTH

VTL

VILMAX

0V

ε

tMSP

CONTROLLER Tx RESET PULSE

CONTROLLER Rx PRESENCE PULSE

RESISTOR (RPUP)

CONTROLLER

1-Wire PERIPHERAL

tF

Figure 3. Initialization Procedure: Reset and Presence Pulse

Read/Write Time Slots

Data communication with the DS28E83 takes place in time slots that carry a single bit each. Write time slots transport

data from bus controller to peripheral. Read time slots transfer data from peripheral to controller. Figure 4 illustrates the

definitions of the write and read time slots.

All communication begins with the controller pulling the data line low. As the voltage on the 1-Wire line falls below the

threshold VTL, the DS28E83 starts its internal timing generator that determines when the data line is sampled during a

write time slot and how long data is valid during a read time slot.

Controller to Peripheral

For a write-one time slot, the voltage on the data line must have crossed the VTH threshold before the write-one low

time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold until

the write-zero low time tW0LMIN is expired. For the most reliable communication, the voltage on the data line should not

exceed VILMAX during the entire tW0L or tW1L window. After the VTH threshold has been crossed, the DS28E83 needs

a recovery time tREC before it is ready for the next time slot.

Peripheral to Controller

A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the read

DS28E83

DeepCover Radiation-Resistant 1-Wire

Authenticator

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