AMIS-710208-A7: 200dpi CIS Module

Data Sheet

9.0 Timing Characteristics

The timing requirements are shown in Figure 4 and Table 6.

Figure 4: Timing Diagram

Table 6: Timing Requirements

Parameters

Symbol

Min.

Typ.

Max.

Units

Clock cycle time

to

0.50

µs

Clock pulse width

tw

62.5

ns

Clock duty cycle

25

50

%

Prohibit crossing time of SP

tprh

15

ns

Data setup time

tds

20

ns

Data hold time

tdh

20

ns

Reset level delay time

tdl

50

ns

Signal sampling time

tsh

120

ns

6

AMI Semiconductor

– Jan. 06, M-20507-001

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