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PCAL6408APW Datasheet(PDF) 21 Page - NXP Semiconductors

Part # PCAL6408APW
Description  Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers
PDF  49 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCAL6408APW Datasheet(HTML) 21 Page - NXP Semiconductors

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PCAL6408A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 18 September 2013
21 of 49
NXP Semiconductors
PCAL6408A
Low-voltage translating, 8-bit I2C-bus/SMBus I/O expander
[1]
Level that VDD(P) can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD <1 s.
[2]
Glitch width that will not cause a functional disruption when
V
DD(gl) =0.5  VDD(P).
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 21 and Table 19 provide more information on
how to measure these specifications.
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD being lowered to or from
0V. Figure 22 and Table 19 provide more details on this specification.
Table 19.
Recommended supply sequencing and ramp rates
Tamb =25 C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(dV/dt)f
fall rate of change of voltage
Figure 19
0.1
-
2000
ms
(dV/dt)r
rise rate of change of voltage
Figure 19
0.1
-
2000
ms
td(rst)
reset delay time
Figure 19; re-ramp time when
VDD(P) drops below 0.2 V or to VSS
1-
-
s
Figure 20; re-ramp time when
VDD(P) drops to VPOR(min)  50 mV
1-
-
s
V
DD(gl)
glitch supply voltage difference
Figure 21
[1] --1.0
V
tw(gl)VDD
supply voltage glitch pulse width
Figure 21
[2] --10
s
VPOR(trip)
power-on reset trip voltage
falling VDD(P)
0.7
--V
rising VDD(P)
--1.4
V
Fig 21. Glitch width and glitch height
Fig 22. Power-on reset voltage (VPOR)
002aag962
VDD(P)
time
tw(gl)VDD
∆VDD(gl)
002aag963
POR
time
VDD(P)
time
VPOR (rising VDD(P))
VPOR (falling VDD(P))



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