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Data Sheet

AD5123/AD5143

THEORY OF OPERATION

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Rev. C | 19 of 25

INPUT SHIFT REGISTER

For the AD5123/AD5143, the input shift register is 16 bits wide, as

shown in Figure 2. The 16-bit word consists of four control bits,

followed by four address bits and by eight data bits.

If the AD5123 RDAC or EEPROM registers are read from or written

to, the lowest data bit (Bit 0) is ignored.

Data is loaded MSB first (Bit 15). The four control bits determine the

function of the software command, as listed in Table 8 and Table 11.

I2C SERIAL DATA INTERFACE

The AD5123/AD5143 have 2-wire, I2C-compatible serial interfaces.

These devices can be connected to an I2C bus as a slave device,

under the control of a master device. See Figure 3 for a timing

diagram of a typical write sequence.

The AD5123/AD5143 support standard (100 kHz) and fast

(400 kHz) data transfer modes. Support is not provided for 10-bit

addressing and general call addressing.

The 2-wire serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition, which is when a high-to-low transition on the SDA

line occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address and an R/W

bit. The slave device corresponding to the transmitted address

responds by pulling SDA low during the ninth clock pulse (this is

called the acknowledge bit). At this stage, all other devices on

the bus remain idle while the selected device waits for data to

be written to, or read from, the shift register.

If the R/W bit is set high, the master reads from the slave

device. However, if the R/W bit is set low, the master writes to

the slave device.

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

The transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of SCL.

3. When all data bits have been read from or written to, a stop

condition is established. In write mode, the master pulls the

SDA line high during the tenth clock pulse to establish a stop

condition. In read mode, the master issues a no acknowledge

for the ninth clock pulse (that is, the SDA line remains high).

The master then brings the SDA line low before the tenth clock

pulse, and then high again during the tenth clock pulse to

establish a stop condition.

I2C ADDRESS

The facility to make hardwired changes to ADDR allows the user to

incorporate up to three of these devices on one bus as outlined in

Table 10.

Table 10. I2C Address Selection

ADDR Pin

7-Bit I2C Device Address

VDD

0101000

No connect1

0101010

GND

0101011

1 Not available in bipolar mode ( VSS < 0 V).

ADVANCED CONTROL MODES

The AD5123/AD5143 digital potentiometers include a set of user

programming features to address the wide number of applications

for these universal adjustment devices (see Table 11 and Table 13).

Key programming features include the following:

►

Input register

►

Linear gain setting mode

►

Low wiper resistance feature

►

Linear increment and decrement instructions

►

±6 dB increment and decrement instructions

►

Burst mode (I2C only)

►

Reset

►

Shutdown mode

Table 11. Advance Commands Operation Truth Table

Command

Number

Control Bits[DB15:DB12]

Address Bits[DB11:DB8]1

Data Bits[DB7:DB0]

Operation

NOP: do nothing

Write contents of serial register data

to RDAC

Write contents of serial register data

to input register

Read back contents

Data

Input register

EEPROM

Control register

RDAC

Linear RDAC increment

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