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DI-40 Datasheet(PDF) 1 Page - Power Integrations, Inc.

Part # DI-40
Description  2.5 V, 20 W DC-DC Converter with Synchronous Rectification
PDF  2 Pages
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Manufacturer  POWERINT [Power Integrations, Inc.]
Direct Link  http://www.powerint.com
Logo POWERINT - Power Integrations, Inc.

DI-40 Datasheet(HTML) 1 Page - Power Integrations, Inc.

  DI-40 Datasheet HTML 1Page - Power Integrations, Inc. DI-40 Datasheet HTML 2Page - Power Integrations, Inc.  
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www.powerint.com
Design Idea DI-40
DPA-Switch 2.5 V, 20 W DC-DC
Converter with Synchronous Rectification
May 2003
DI-40
Application
DC-DC Converter
DPA424R
2.5 V
Power Output
20 W
Input Voltage
Output Voltage
Topology
Device
36-75 VDC
Forward
Figure 1. DPA-Switch 20 W DC to DC Converter.
.
Design Highlights
• Extremely low component count
• High efficiency - 86% using synchronous rectification
• No current sense resistor or current transformer required
• Output overload, open loop and thermal protection
• Accurate input under/overvoltage meets ETSI standards
• 300 kHz switching frequency - optimizes efficiency when
simple self-driven synchronous rectification is used
Operation
DPA-Switch greatly simplifies the design compared to a discrete
implementation. Resistor R1 programs the input UV/OV
thresholds. The tight tolerance of the UV/OV thresholds limits
the range of gate drive voltages applied to MOSFETs Q1 and
Q2, eliminating the need for gate voltage clamp circuitry. The
self-driven synchronous rectification configuration is therefore
very simple, with R13 filtering voltage spikes at the gate of Q2,
and D3 preventing the body diode of Q1 from conducting.
Capacitor C8 and the gate capacitance of Q1 reset T1 during
DPA-Switch off-time. Zener VR1 provides a hard voltage
clamp to limit DRAIN voltage under output transient and
overload conditions.
Since the output voltage is low, the U2 LED is supplied with
a higher voltage derived from a winding on output choke L2.
The DPA-Switch bias supply is derived from a forward
winding on transformer T1. Flyback windings are not
recommended for this purpose, since the bias capacitor C4
would create high capacitive loading during DPA-Switch
off- time, preventing the transformer from efficiently resetting.
Key Design Points
• For
nominal
under-voltage
set
point
V
UV:
R1=(V
UV- 2.35 V)/50 µA. VOV = (R1 x 135 µA)+2.5 V.
• Locate C5, C6, and R4 close to U1 CONTROL pin, with
ground connected to SOURCE pin.
•Minimize primary and secondary layout loop area to
reduce parasitic inductance.
®
C5
0.22 µF
VR1
SMBJ150
C6
68 µF
10 V
D3
12CWQ03FM
C4
1 µF
R3
15 kΩ
1%
R4
1.0 Ω
C9, C10
100 µF
10 V
C11
1 µF
10 V
36 - 75 VDC
L1
1 µH 2.5 A
L2
3.3 µH
8 A
L3
2.2 mH
40 mA
PI-3264-051303
DPA-Switch
2.5 V, 8 A
R13
10 Ω
U1
DPA424R
1
4
6, 7
2
3
C7
1 nF
1.5 kV
R1
619 kΩ
T1
R5
1.0 Ω
D
S
C
CONTROL
L
F
X
U2
PC357
N1T
9, 10
C8
2.2 nF
C12
4.7 µF
20 V
D2
BAV19WS
7, 8
2
1
5, 6
RTN
C1, C2
1 µF
100 V
Q1
SI4842DY
Q2
SI4842DY
D1
BAV19WS
R14
10 Ω
V
IN
+
V
IN
U2
D3
BAV19WS
U3
LMV431
AIM5X
R9
220 Ω
R11
10.0 kΩ
1%
R10
10.2 kΩ
1%
R12
5.1 Ω
R7
10 kΩ
C14
1 µF
C15
10 µF
10 V
C13
100 nF
R6
150 Ω
C3
1 µF
100 V
D4
BAV19WS


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