Design Idea DI-128

35 W (75 W Peak) Variable-speed

DC Motor Drive

Figure 1. Circuit Diagram of 35 W Continuous, 75 W Peak, Motor Drive Power Supply with Dual Speed Control Inputs.

DI-128

November 2006

Application

Device

Power Output

Input Voltage

Output Voltage

Topology

DC Motor Drive

PKS606Y

35 W (75 W Pk)

90-265 VAC

12 V

Flyback

Design Highlights

• Replaces a two-stage, linear power supply and chopper

circuit with a simple, single-stage design

• Eliminates the chopper circuits normally used to

achieve variable-speed control of DC motors

• Motor speed is controllable by a small potentiometer or

a 3.6 V to 10 V variable DC voltage

• Low component count: only 47 parts

• Efficiency: ≥77% (at a load of 35 W)

• Meets EN55022 B conducted EMI limits

• ON/OFF control scheme is stable over the entire motor

speed (output voltage) range

Operation

The flyback converter shown in Figure 1 uses a member of

the PeakSwitch family (U1, a PKS606Y) to drive a 35 W

motor, while delivering startup and load transition peaks of

up to 75 W. The motorʼs speed is variable by two methods:

1) potentiometer R20 (connected to J3), or 2) an externally

supplied3.6Vto10VDCvoltagesource(connectedtoJ4). The

motor speed controls vary the output voltage of the supply.

The controller in U1 receives feedback from the output and

enables or disables the switching of its integrated MOSFET.

Regulation is maintained by disabling or skipping MOSFET

switching cycles. The output voltage is sensed across the

series string of R12, Zener diode VR2 and the LED in U2

(in parallel with R13). As the output voltage rises above the

VR2 conduction threshold, the current that flows through the

U2 LED turns on transistor Q3. As Q3 pulls current out of

the EN/UV pin of U1 switching cycles are skipped and less

energy is transferred to the output. Once the output voltage

falls, switching cycles are enabled again.

Abiaswinding(T1,pins4and5)onthetransformerisrectified

and filtered by D7 and C6, and supplies operating current to

U1, through R7. AsmartAC sense circuit–comprised of D5,

C7, R5 and R6–enables the under-voltage lockout (UVLO)

and latching shutdown functions of U1. The frequency jitter

D1-D4

1N4007

D5

1N4007

D7

1N4148

D8

MBR1060

VR2

1N5222B

2.5 V

L1

5.3 mH

1 A

R1 & R2

1.3 M

Ω

R15

2.2

Ω

1/8 W

R3

150

Ω

1/2 W

R18

20

Ω

1/8 W

R7

4.7 k

Ω

R5

2.2 M

Ω

R6

2.4 M

Ω

U2B

PC817X4

C10

1 nF

250 VAC

C3

680 nF

275 VAC

C2,C1

100 pF

275 VAC

C17

4700 pF

1 kV

C7

100 nF

400 V

C4

180

µF

400 V

C5

470 pF

1 kV

C20

680

µF

25 V

C12

680

µF

25 V

C21

1.0

µF

50 V

U2A

PC817X4

+12 V

J3-1

J3-2

J2-1

J2-2

J4-1

J4-2

RTN

C15

100 nF

50 V

VR1

P6KE200A

200 V

D6

FR106

D12

1N4148

C11

330 pF

1 kV

C8

220 nF

50 V

C19

1 nF

250 VAC

C6

47

µF

35 V

Q3

2N3904

R8

68

Ω

1/2 W

R19

2 k

Ω

R20

5 k

Ω

R13

1 k

Ω

1

9,10

7,8

5

4

3

2

F1

3.15 A

CON3

PI-4519-110606

U1

PKS606Y

PeakSwitch

D

S

EN/UV

BP

GND

H PE L

MOTOR

RT1

10

Ω

JP2

JP1

JP3

R12

4.99 k

Ω

1%

+